| Message ID | 1666935144-7364-2-git-send-email-shengjiu.wang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: imx8mp: Add audio shared gate | expand |
On 22-10-28 13:32:23, Shengjiu Wang wrote: > From: Abel Vesa <abel.vesa@nxp.com> > > All these IDs are for one single HW gate (CCGR101) that is shared > between these root clocks. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > include/dt-bindings/clock/imx8mp-clock.h | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h > index 9d5cc2ddde89..2f6fec299662 100644 > --- a/include/dt-bindings/clock/imx8mp-clock.h > +++ b/include/dt-bindings/clock/imx8mp-clock.h > @@ -324,8 +324,17 @@ > #define IMX8MP_CLK_CLKOUT2_SEL 317 > #define IMX8MP_CLK_CLKOUT2_DIV 318 > #define IMX8MP_CLK_CLKOUT2 319 > +#define IMX8MP_CLK_AUDIO_AHB_ROOT 320 > +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 > +#define IMX8MP_CLK_SAI1_ROOT 322 > +#define IMX8MP_CLK_SAI2_ROOT 323 > +#define IMX8MP_CLK_SAI3_ROOT 324 > +#define IMX8MP_CLK_SAI5_ROOT 325 > +#define IMX8MP_CLK_SAI6_ROOT 326 > +#define IMX8MP_CLK_SAI7_ROOT 327 > +#define IMX8MP_CLK_PDM_ROOT 328 > > -#define IMX8MP_CLK_END 320 > +#define IMX8MP_CLK_END 329 > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 > -- > 2.34.1 >
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 9d5cc2ddde89..2f6fec299662 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,8 +324,17 @@ #define IMX8MP_CLK_CLKOUT2_SEL 317 #define IMX8MP_CLK_CLKOUT2_DIV 318 #define IMX8MP_CLK_CLKOUT2 319 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 320 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 +#define IMX8MP_CLK_SAI1_ROOT 322 +#define IMX8MP_CLK_SAI2_ROOT 323 +#define IMX8MP_CLK_SAI3_ROOT 324 +#define IMX8MP_CLK_SAI5_ROOT 325 +#define IMX8MP_CLK_SAI6_ROOT 326 +#define IMX8MP_CLK_SAI7_ROOT 327 +#define IMX8MP_CLK_PDM_ROOT 328 -#define IMX8MP_CLK_END 320 +#define IMX8MP_CLK_END 329 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1