diff mbox series

[v6,2/6] arm64: dts: Add i.MX8MM PCIe EP support on EVK board

Message ID 1674192352-4473-3-git-send-email-hongxing.zhu@nxp.com (mailing list archive)
State New, archived
Headers show
Series Add i.MX PCIe EP mode support | expand

Commit Message

Richard Zhu Jan. 20, 2023, 5:25 a.m. UTC
Add i.MX8MM PCIe EP support on EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Krzysztof Kozlowski Jan. 20, 2023, 8:08 a.m. UTC | #1
On 20/01/2023 06:25, Richard Zhu wrote:
> Add i.MX8MM PCIe EP support on EVK board.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 0ce3005d578d..9d65b70939fa 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -371,6 +371,19 @@ &pcie0 {
>  	status = "okay";
>  };
>  
> +&pcie0_ep{
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pcie0>;
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> +	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> +			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
> +	assigned-clock-rates = <10000000>, <250000000>;
> +	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
> +				 <&clk IMX8MM_SYS_PLL2_250M>;
> +	status = "disabled";

It's already disabled. What are you doing here? Having disabled node is
useless, so entire patch should be dropped.

Best regards,
Krzysztof
Richard Zhu Jan. 30, 2023, 2:02 a.m. UTC | #2
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2023年1月20日 16:09
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org; Peng Fan
> <peng.fan@nxp.com>; marex@denx.de; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; tharvey@gateworks.com; Frank Li
> <frank.li@nxp.com>
> Cc: lorenzo.pieralisi@arm.com; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v6 2/6] arm64: dts: Add i.MX8MM PCIe EP support on EVK
> board
> 
> On 20/01/2023 06:25, Richard Zhu wrote:
> > Add i.MX8MM PCIe EP support on EVK board.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > index 0ce3005d578d..9d65b70939fa 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > @@ -371,6 +371,19 @@ &pcie0 {
> >  	status = "okay";
> >  };
> >
> > +&pcie0_ep{
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_pcie0>;
> > +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> > +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> > +	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> > +			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
> > +	assigned-clock-rates = <10000000>, <250000000>;
> > +	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
> > +				 <&clk IMX8MM_SYS_PLL2_250M>;
> > +	status = "disabled";
> 
> It's already disabled. What are you doing here? Having disabled node is useless,
> so entire patch should be dropped.
Okay, the 2/4/6 patches would be dropped. Thanks.

Best Regards
Richard Zhu
> 
> Best regards,
> Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 0ce3005d578d..9d65b70939fa 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -371,6 +371,19 @@  &pcie0 {
 	status = "okay";
 };
 
+&pcie0_ep{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	status = "disabled";
+};
+
 &sai2 {
 	#sound-dai-cells = <0>;
 	pinctrl-names = "default";