| Message ID | 1675323337-19358-2-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add i.MX PCIe EP mode support | expand |
On 02/02/2023 08:35, Richard Zhu wrote: > Restruct i.MX PCIe schema, derive the common properties, thus they can > be shared by both the RC and Endpoint schema. > > Update the description of fsl,imx6q-pcie.yaml, and move the EP mode > compatible to fsl,imx6q-pcie-ep.yaml. > > Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER > accordingly. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 285 ++++++++++++++++++ > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 83 +++++ > .../bindings/pci/fsl,imx6q-pcie.yaml | 247 +-------------- > MAINTAINERS | 2 + > 4 files changed, 376 insertions(+), 241 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > new file mode 100644 > index 000000000000..f291f7529622 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > @@ -0,0 +1,285 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX6 PCIe RC/EP controller > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + - Richard Zhu <hongxing.zhu@nxp.com> > + > +description: > + Generic Freescale i.MX PCIe Root Port and Endpoint controller > + properties. > + > +properties: > + compatible: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6sx-pcie > + - fsl,imx6qp-pcie > + - fsl,imx7d-pcie > + - fsl,imx8mq-pcie > + - fsl,imx8mm-pcie > + - fsl,imx8mp-pcie > + - fsl,imx8mm-pcie-ep > + - fsl,imx8mq-pcie-ep > + - fsl,imx8mp-pcie-ep Compatibles are not part of common schema. Are you saying that EP compatible is valid for PCIE not working as endpoint? This does not make sense. The common part is only the part which is common. Compatible is not common, not shared. Also missing required: block. (...) > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > new file mode 100644 > index 000000000000..f651bc3fcaf7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX6 PCIe Endpoint controller > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + - Richard Zhu <hongxing.zhu@nxp.com> > + > +description: |+ > + This PCIe controller is based on the Synopsys DesignWare PCIe IP and > + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. > + The controller instances are dual mode where in they can work either in > + Root Port mode or Endpoint mode but one at a time. > + > +properties: > + reg: > + minItems: 2 > + > + reg-names: > + items: > + - const: dbi > + - const: addr_space > + > + interrupts: > + items: > + - description: builtin eDMA interrupter. > + > + interrupt-names: > + items: > + - const: dma > + > +required: > + - compatible > + - reg > + - reg-names > + - num-lanes > + - interrupts > + - interrupt-names > + - clocks > + - clock-names Several of these should be required by common schema/ > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> > + #include <dt-bindings/power/imx8mp-power.h> > + #include <dt-bindings/reset/imx8mp-reset.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + pcie_ep: pcie-ep@33800000 { > + compatible = "fsl,imx8mp-pcie-ep"; > + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; > + reg-names = "dbi", "addr_space"; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>, > + <&clk IMX8MP_CLK_PCIE_ROOT>; > + clock-names = "pcie", "pcie_bus", "pcie_aux"; > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates = <10000000>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > + num-lanes = <1>; > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ > + interrupt-names = "dma"; > + fsl,max-link-speed = <3>; > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > + reset-names = "apps", "turnoff"; > + phys = <&pcie_phy>; > + phy-names = "pcie-phy"; > + num-ib-windows = <4>; > + num-ob-windows = <4>; > + status = "disabled"; Drop status > + }; > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index f13f87fddb3d..db1d0a04bde4 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -13,21 +13,13 @@ maintainers: > description: |+ > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > and thus inherits all the common properties defined in snps,dw-pcie.yaml. > + The controller instances are dual mode where in they can work either in > + Root Port mode or Endpoint mode but one at a time. > > -properties: > - compatible: > - enum: > - - fsl,imx6q-pcie > - - fsl,imx6sx-pcie > - - fsl,imx6qp-pcie > - - fsl,imx7d-pcie > - - fsl,imx8mq-pcie > - - fsl,imx8mm-pcie > - - fsl,imx8mp-pcie Compatibles should stay because these are not valid for EP schema. > - - fsl,imx8mm-pcie-ep > - - fsl,imx8mq-pcie-ep > - - fsl,imx8mp-pcie-ep > + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree > + bindings. > Best regards, Krzysztof
Hi Krzysztof: Thanks for your review comments. > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: 2023年2月3日 4:31 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; l.stach@pengutronix.de; > shawnguo@kernel.org; lorenzo.pieralisi@arm.com; Peng Fan > <peng.fan@nxp.com>; marex@denx.de; Marcel Ziswiler > <marcel.ziswiler@toradex.com>; tharvey@gateworks.com; Frank Li > <frank.li@nxp.com> > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v9 1/4] dt-bindings: imx6q-pcie: Restruct i.MX PCIe > schema > > On 02/02/2023 08:35, Richard Zhu wrote: > > Restruct i.MX PCIe schema, derive the common properties, thus they can > > be shared by both the RC and Endpoint schema. > > > > Update the description of fsl,imx6q-pcie.yaml, and move the EP mode > > compatible to fsl,imx6q-pcie-ep.yaml. > > > > Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER > > accordingly. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > --- > > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 285 > ++++++++++++++++++ > > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 83 +++++ > > .../bindings/pci/fsl,imx6q-pcie.yaml | 247 +-------------- > > MAINTAINERS | 2 + > > 4 files changed, 376 insertions(+), 241 deletions(-) create mode > > 100644 > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > > create mode 100644 > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > > new file mode 100644 > > index 000000000000..f291f7529622 > > --- /dev/null > > +++ > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml > > @@ -0,0 +1,285 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie-common.yaml%23&dat > a=05% > > > +7C01%7Chongxing.zhu%40nxp.com%7Cbc4ab9b963194b84cfb408db055c79 > 30%7C68 > > > +6ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638109666953361711% > 7CUnknown > > > +%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > WwiLC > > > +JXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=xbM1eZn2swqrsdlwpNA4eCe > KTdVWTL3RU9 > > +78v7d0DMU%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chongxin > g.zhu% > > > +40nxp.com%7Cbc4ab9b963194b84cfb408db055c7930%7C686ea1d3bc2b4c > 6fa92cd9 > > > +9c5c301635%7C0%7C0%7C638109666953361711%7CUnknown%7CTWFpb > GZsb3d8eyJWI > > > +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000% > > > +7C%7C%7C&sdata=%2F%2FCEvu0g51SzeBXDToMlYrefPYbBWARm1FqQVai7x > Bc%3D&res > > +erved=0 > > + > > +title: Freescale i.MX6 PCIe RC/EP controller > > + > > +maintainers: > > + - Lucas Stach <l.stach@pengutronix.de> > > + - Richard Zhu <hongxing.zhu@nxp.com> > > + > > +description: > > + Generic Freescale i.MX PCIe Root Port and Endpoint controller > > + properties. > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx6q-pcie > > + - fsl,imx6sx-pcie > > + - fsl,imx6qp-pcie > > + - fsl,imx7d-pcie > > + - fsl,imx8mq-pcie > > + - fsl,imx8mm-pcie > > + - fsl,imx8mp-pcie > > + - fsl,imx8mm-pcie-ep > > + - fsl,imx8mq-pcie-ep > > + - fsl,imx8mp-pcie-ep > > Compatibles are not part of common schema. Are you saying that EP > compatible is valid for PCIE not working as endpoint? This does not make > sense. The common part is only the part which is common. Compatible is not > common, not shared. > Okay, would sperate the compatibles by RC ane EP. > > Also missing required: block. > Would add the common required: block too. Since the RC and EP schema has different description of the reg/reg-names/interrupts... Is it fine to let RC or EP schema has its own reg/reg-names/interrupts... properties? > (...) > > > diff --git > > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > > new file mode 100644 > > index 000000000000..f651bc3fcaf7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml > > @@ -0,0 +1,83 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie-ep.yaml%23&data=05 > %7C01 > > > +%7Chongxing.zhu%40nxp.com%7Cbc4ab9b963194b84cfb408db055c7930% > 7C686ea1 > > > +d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638109666953361711%7CU > nknown%7CT > > > +WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL > CJXVC > > > +I6Mn0%3D%7C3000%7C%7C%7C&sdata=4UbTmbEFMOn9nDEO4WwVoheX > tl2zk%2BAo%2Ff > > +rbonvl0yo%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chongxin > g.zhu% > > > +40nxp.com%7Cbc4ab9b963194b84cfb408db055c7930%7C686ea1d3bc2b4c > 6fa92cd9 > > > +9c5c301635%7C0%7C0%7C638109666953361711%7CUnknown%7CTWFpb > GZsb3d8eyJWI > > > +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000% > > > +7C%7C%7C&sdata=%2F%2FCEvu0g51SzeBXDToMlYrefPYbBWARm1FqQVai7x > Bc%3D&res > > +erved=0 > > + > > +title: Freescale i.MX6 PCIe Endpoint controller > > + > > +maintainers: > > + - Lucas Stach <l.stach@pengutronix.de> > > + - Richard Zhu <hongxing.zhu@nxp.com> > > + > > +description: |+ > > + This PCIe controller is based on the Synopsys DesignWare PCIe IP > > +and > > + thus inherits all the common properties defined in > snps,dw-pcie-ep.yaml. > > + The controller instances are dual mode where in they can work > > +either in > > + Root Port mode or Endpoint mode but one at a time. > > + > > +properties: > > + reg: > > + minItems: 2 > > + > > + reg-names: > > + items: > > + - const: dbi > > + - const: addr_space > > + > > + interrupts: > > + items: > > + - description: builtin eDMA interrupter. > > + > > + interrupt-names: > > + items: > > + - const: dma > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - num-lanes > > + - interrupts > > + - interrupt-names > > + - clocks > > + - clock-names > > Several of these should be required by common schema/ How about this definitions of the required: block? <for common> required: - num-lanes - clocks - clock-names - power-domains - power-domain-names - resets - reset-names <for ep> required: - compatible - reg - reg-names - interrupts - interrupt-names <for rc> required: - compatible - reg - reg-names - "#address-cells" - "#size-cells" - device_type - bus-range - ranges - interrupts - interrupt-names - "#interrupt-cells" - interrupt-map-mask - interrupt-map > > > + > > +allOf: > > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > > + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/imx8mp-clock.h> > > + #include <dt-bindings/power/imx8mp-power.h> > > + #include <dt-bindings/reset/imx8mp-reset.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + pcie_ep: pcie-ep@33800000 { > > + compatible = "fsl,imx8mp-pcie-ep"; > > + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; > > + reg-names = "dbi", "addr_space"; > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > > + <&clk IMX8MP_CLK_HSIO_AXI>, > > + <&clk IMX8MP_CLK_PCIE_ROOT>; > > + clock-names = "pcie", "pcie_bus", "pcie_aux"; > > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > > + assigned-clock-rates = <10000000>; > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > > + num-lanes = <1>; > > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ > > + interrupt-names = "dma"; > > + fsl,max-link-speed = <3>; > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > > + reset-names = "apps", "turnoff"; > > + phys = <&pcie_phy>; > > + phy-names = "pcie-phy"; > > + num-ib-windows = <4>; > > + num-ob-windows = <4>; > > + status = "disabled"; > > Drop status Okay. > > > + }; > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > index f13f87fddb3d..db1d0a04bde4 100644 > > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > @@ -13,21 +13,13 @@ maintainers: > > description: |+ > > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > > and thus inherits all the common properties defined in > snps,dw-pcie.yaml. > > + The controller instances are dual mode where in they can work > > + either in Root Port mode or Endpoint mode but one at a time. > > > > -properties: > > - compatible: > > - enum: > > - - fsl,imx6q-pcie > > - - fsl,imx6sx-pcie > > - - fsl,imx6qp-pcie > > - - fsl,imx7d-pcie > > - - fsl,imx8mq-pcie > > - - fsl,imx8mm-pcie > > - - fsl,imx8mp-pcie > > Compatibles should stay because these are not valid for EP schema. Okay. Best Regards Richard Zhu > > > - - fsl,imx8mm-pcie-ep > > - - fsl,imx8mq-pcie-ep > > - - fsl,imx8mp-pcie-ep > > + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device > > + tree bindings. > > > > > Best regards, > Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml new file mode 100644 index 000000000000..f291f7529622 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 PCIe RC/EP controller + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + - Richard Zhu <hongxing.zhu@nxp.com> + +description: + Generic Freescale i.MX PCIe Root Port and Endpoint controller + properties. + +properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + + clocks: + minItems: 3 + items: + - description: PCIe bridge clock. + - description: PCIe bus clock. + - description: PCIe PHY clock. + - description: Additional required clock entry for imx6sx-pcie, + imx8mq-pcie. + + clock-names: + minItems: 3 + items: + - const: pcie + - const: pcie_bus + - enum: [ pcie_phy, pcie_aux ] + - enum: [ pcie_inbound_axi, pcie_aux ] + + num-lanes: + const: 1 + + fsl,imx7d-pcie-phy: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to an fsl,imx7d-pcie-phy node. Additional + required properties for imx7d-pcie and imx8mq-pcie. + + power-domains: + minItems: 1 + items: + - description: The phandle pointing to the DISPLAY domain for + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and + imx8mq-pcie. + - description: The phandle pointing to the PCIE_PHY power domains + for imx6sx-pcie. + + power-domain-names: + minItems: 1 + items: + - const: pcie + - const: pcie_phy + + resets: + minItems: 2 + maxItems: 3 + description: Phandles to PCIe-related reset lines exposed by SRC + IP block. Additional required by imx7d-pcie and imx8mq-pcie. + + reset-names: + minItems: 2 + maxItems: 3 + + fsl,tx-deemph-gen1: + description: Gen1 De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-3p5db: + description: Gen2 (3.5db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-6db: + description: Gen2 (6db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 20 + + fsl,tx-swing-full: + description: Gen2 TX SWING FULL value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,tx-swing-low: + description: TX launch amplitude swing_low value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,max-link-speed: + description: Specify PCI Gen for link capability (optional required). + Note that the IMX6 LVDS clock outputs do not meet gen2 jitter + requirements and thus for gen2 capability a gen2 compliant clock + generator should be used and configured. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + vpcie-supply: + description: Should specify the regulator in charge of PCIe port power. + The regulator will be enabled when initializing the PCIe host and + disabled either as part of the init process or when shutting down + the host (optional required). + + vph-supply: + description: Should specify the regulator in charge of VPH one of + the three PCIe PHY powers. This regulator can be supplied by both + 1.8v and 3.3v voltage supplies (optional required). + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx6sx-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_inbound_axi + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-pcie + - fsl,imx8mq-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_aux + - if: + properties: + compatible: + not: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx8mq-pcie + - fsl,imx6sx-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_phy + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_aux + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: false + power-domain-names: false + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx6sx-pcie-ep + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: false + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6sx-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + resets: + minItems: 3 + reset-names: + items: + - const: pciephy + - const: apps + - const: turnoff + else: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: apps + - const: turnoff + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml new file mode 100644 index 000000000000..f651bc3fcaf7 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 PCIe Endpoint controller + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + - Richard Zhu <hongxing.zhu@nxp.com> + +description: |+ + This PCIe controller is based on the Synopsys DesignWare PCIe IP and + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + +properties: + reg: + minItems: 2 + + reg-names: + items: + - const: dbi + - const: addr_space + + interrupts: + items: + - description: builtin eDMA interrupter. + + interrupt-names: + items: + - const: dma + +required: + - compatible + - reg + - reg-names + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> + #include <dt-bindings/reset/imx8mp-reset.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f13f87fddb3d..db1d0a04bde4 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -13,21 +13,13 @@ maintainers: description: |+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. -properties: - compatible: - enum: - - fsl,imx6q-pcie - - fsl,imx6sx-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - - fsl,imx8mq-pcie - - fsl,imx8mm-pcie - - fsl,imx8mp-pcie - - fsl,imx8mm-pcie-ep - - fsl,imx8mq-pcie-ep - - fsl,imx8mp-pcie-ep + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree + bindings. +properties: reg: items: - description: Data Bus Interface (DBI) registers. @@ -46,96 +38,6 @@ properties: items: - const: msi - clocks: - minItems: 3 - items: - - description: PCIe bridge clock. - - description: PCIe bus clock. - - description: PCIe PHY clock. - - description: Additional required clock entry for imx6sx-pcie, - imx8mq-pcie. - - clock-names: - minItems: 3 - items: - - const: pcie - - const: pcie_bus - - enum: [ pcie_phy, pcie_aux ] - - enum: [ pcie_inbound_axi, pcie_aux ] - - num-lanes: - const: 1 - - fsl,imx7d-pcie-phy: - $ref: /schemas/types.yaml#/definitions/phandle - description: A phandle to an fsl,imx7d-pcie-phy node. Additional - required properties for imx7d-pcie and imx8mq-pcie. - - power-domains: - minItems: 1 - items: - - description: The phandle pointing to the DISPLAY domain for - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and - imx8mq-pcie. - - description: The phandle pointing to the PCIE_PHY power domains - for imx6sx-pcie. - - power-domain-names: - minItems: 1 - items: - - const: pcie - - const: pcie_phy - - resets: - minItems: 2 - maxItems: 3 - description: Phandles to PCIe-related reset lines exposed by SRC - IP block. Additional required by imx7d-pcie and imx8mq-pcie. - - reset-names: - minItems: 2 - maxItems: 3 - - fsl,tx-deemph-gen1: - description: Gen1 De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - fsl,tx-deemph-gen2-3p5db: - description: Gen2 (3.5db) De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - fsl,tx-deemph-gen2-6db: - description: Gen2 (6db) De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 20 - - fsl,tx-swing-full: - description: Gen2 TX SWING FULL value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 127 - - fsl,tx-swing-low: - description: TX launch amplitude swing_low value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 127 - - fsl,max-link-speed: - description: Specify PCI Gen for link capability (optional required). - Note that the IMX6 LVDS clock outputs do not meet gen2 jitter - requirements and thus for gen2 capability a gen2 compliant clock - generator should be used and configured. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 3, 4] - default: 1 - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset @@ -147,17 +49,6 @@ properties: L=operation state) (optional required). type: boolean - vpcie-supply: - description: Should specify the regulator in charge of PCIe port power. - The regulator will be enabled when initializing the PCIe host and - disabled either as part of the init process or when shutting down - the host (optional required). - - vph-supply: - description: Should specify the regulator in charge of VPH one of - the three PCIe PHY powers. This regulator can be supplied by both - 1.8v and 3.3v voltage supplies (optional required). - required: - compatible - reg @@ -178,133 +69,7 @@ required: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - - if: - properties: - compatible: - contains: - const: fsl,imx6sx-pcie - then: - properties: - clock-names: - items: - - {} - - {} - - const: pcie_phy - - const: pcie_inbound_axi - power-domains: - minItems: 2 - power-domain-names: - minItems: 2 - - if: - properties: - compatible: - contains: - const: fsl,imx8mq-pcie - then: - properties: - clock-names: - items: - - {} - - {} - - const: pcie_phy - - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - then: - properties: - clock-names: - maxItems: 3 - contains: - const: pcie_phy - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx8mm-pcie - - fsl,imx8mp-pcie - then: - properties: - clock-names: - maxItems: 3 - contains: - const: pcie_aux - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - then: - properties: - power-domains: false - power-domain-names: false - - - if: - not: - properties: - compatible: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - then: - properties: - power-domains: - maxItems: 1 - power-domain-names: false - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6sx-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - - fsl,imx8mq-pcie - then: - properties: - resets: - minItems: 3 - reset-names: - items: - - const: pciephy - - const: apps - - const: turnoff - else: - properties: - resets: - maxItems: 2 - reset-names: - items: - - const: apps - - const: turnoff + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# unevaluatedProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 5dce1c45f4d1..5ee8de98d4a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15997,6 +15997,8 @@ M: Lucas Stach <l.stach@pengutronix.de> L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml F: drivers/pci/controller/dwc/*imx6*
Restruct i.MX PCIe schema, derive the common properties, thus they can be shared by both the RC and Endpoint schema. Update the description of fsl,imx6q-pcie.yaml, and move the EP mode compatible to fsl,imx6q-pcie-ep.yaml. Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER accordingly. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- .../bindings/pci/fsl,imx6q-pcie-common.yaml | 285 ++++++++++++++++++ .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 83 +++++ .../bindings/pci/fsl,imx6q-pcie.yaml | 247 +-------------- MAINTAINERS | 2 + 4 files changed, 376 insertions(+), 241 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml