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Sat, 9 Sep 2023 20:18:14 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Sat, 9 Sep 2023 13:18:04 -0700 From: Mukesh Ojha To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v5 10/17] pstore: Add pstore_region_defined() helper and export it Date: Sun, 10 Sep 2023 01:46:11 +0530 Message-ID: <1694290578-17733-11-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1694290578-17733-1-git-send-email-quic_mojha@quicinc.com> References: <1694290578-17733-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dIWnjtDaYbpMoOmHa-qDFqETXv0l5IcY X-Proofpoint-GUID: dIWnjtDaYbpMoOmHa-qDFqETXv0l5IcY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-09_19,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 malwarescore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309090187 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230909_131840_544747_2DE4182F X-CRM114-Status: GOOD ( 21.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There are users like Qualcomm minidump which is interested in knowing the pstore frontend addresses and sizes from the backend (ram) to be able to register it with firmware to finally collect them during crash for debugging. Signed-off-by: Mukesh Ojha --- fs/pstore/platform.c | 15 +++++++++++++++ fs/pstore/ram.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pstore.h | 6 ++++++ 3 files changed, 63 insertions(+) diff --git a/fs/pstore/platform.c b/fs/pstore/platform.c index cbc0b468c1ab..cb80116a05cb 100644 --- a/fs/pstore/platform.c +++ b/fs/pstore/platform.c @@ -137,6 +137,21 @@ enum pstore_type_id pstore_name_to_type(const char *name) } EXPORT_SYMBOL_GPL(pstore_name_to_type); +int pstore_region_defined(struct pstore_record *record, + void **virt, phys_addr_t *phys, + size_t *size, unsigned int *max_dump_cnt) +{ + if (!psinfo) + return -EINVAL; + + record->psi = psinfo; + + return psinfo->region_info ? + psinfo->region_info(record, virt, phys, size, max_dump_cnt) : + -EINVAL; +} +EXPORT_SYMBOL_GPL(pstore_region_defined); + static void pstore_timer_kick(void) { if (pstore_update_ms < 0) diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c index e73fbbc1b5b5..2ebb1f5f6350 100644 --- a/fs/pstore/ram.c +++ b/fs/pstore/ram.c @@ -436,6 +436,47 @@ static int ramoops_pstore_erase(struct pstore_record *record) return 0; } +static int ramoops_region_info(struct pstore_record *record, + void **virt, phys_addr_t *phys, + size_t *size, unsigned int *max_dump_cnt) +{ + struct ramoops_context *cxt = record->psi->data; + struct persistent_ram_zone *prz; + + switch (record->type) { + case PSTORE_TYPE_DMESG: + if (record->id >= cxt->max_dump_cnt) + return -EINVAL; + prz = cxt->dprzs[record->id]; + *max_dump_cnt = cxt->max_dump_cnt; + break; + case PSTORE_TYPE_CONSOLE: + if (!cxt->console_size) + return -EINVAL; + prz = cxt->cprz; + break; + case PSTORE_TYPE_FTRACE: + if (record->id >= cxt->max_ftrace_cnt) + return -EINVAL; + prz = cxt->fprzs[record->id]; + *max_dump_cnt = cxt->max_ftrace_cnt; + break; + case PSTORE_TYPE_PMSG: + if (!cxt->pmsg_size) + return -EINVAL; + prz = cxt->mprz; + break; + default: + return -EINVAL; + } + + *virt = prz->vaddr; + *phys = prz->paddr; + *size = prz->size; + + return 0; +} + static struct ramoops_context oops_cxt = { .pstore = { .owner = THIS_MODULE, @@ -445,6 +486,7 @@ static struct ramoops_context oops_cxt = { .write = ramoops_pstore_write, .write_user = ramoops_pstore_write_user, .erase = ramoops_pstore_erase, + .region_info = ramoops_region_info, }, }; diff --git a/include/linux/pstore.h b/include/linux/pstore.h index 638507a3c8ff..a64d866e8711 100644 --- a/include/linux/pstore.h +++ b/include/linux/pstore.h @@ -199,6 +199,9 @@ struct pstore_info { int (*write_user)(struct pstore_record *record, const char __user *buf); int (*erase)(struct pstore_record *record); + int (*region_info)(struct pstore_record *record, + void **virt, phys_addr_t *phys, + size_t *size, unsigned int *max_dump_cnt); }; /* Supported frontends */ @@ -230,6 +233,9 @@ struct pstore_ftrace_record { #define TS_CPU_SHIFT 8 #define TS_CPU_MASK (BIT(TS_CPU_SHIFT) - 1) +int pstore_region_defined(struct pstore_record *record, + void **virt, phys_addr_t *phys, + size_t *size, unsigned int *max_dump_cnt); /* * If CPU number can be stored in IP, store it there, otherwise store it in * the time stamp. This means more timestamp resolution is available when