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Fri, 19 Jan 2024 03:23:37 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 18 Jan 2024 19:23:32 -0800 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Song Chai , , Subject: [PATCH v4 02/10] coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset Date: Fri, 19 Jan 2024 11:22:55 +0800 Message-ID: <1705634583-17631-3-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705634583-17631-1-git-send-email-quic_taozha@quicinc.com> References: <1705634583-17631-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: f5gS4_gH0DDIlFLu9-YNT77bDMjWbbpc X-Proofpoint-ORIG-GUID: f5gS4_gH0DDIlFLu9-YNT77bDMjWbbpc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_12,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190012 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240118_192347_616605_64C109C2 X-CRM114-Status: GOOD ( 20.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since the function tpdm_has_dsb_dataset will be called by TPDA driver in subsequent patches, it is moved to the header file. And move this judgement form the function __tpdm_{enable/disable} to the beginning of the function tpdm_{enable/disable}_dsb. Signed-off-by: Tao Zhang --- drivers/hwtracing/coresight/coresight-tpdm.c | 82 ++++++++++---------- drivers/hwtracing/coresight/coresight-tpdm.h | 4 + 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 0427c0fc0bf3..6549f71ba150 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -125,11 +125,6 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, return ret; } -static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) -{ - return (drvdata->datasets & TPDM_PIDR0_DS_DSB); -} - static umode_t tpdm_dsb_is_visible(struct kobject *kobj, struct attribute *attr, int n) { @@ -232,38 +227,39 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; - for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) - writel_relaxed(drvdata->dsb->edge_ctrl[i], - drvdata->base + TPDM_DSB_EDCR(i)); - for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) - writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], - drvdata->base + TPDM_DSB_EDCMR(i)); - for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { - writel_relaxed(drvdata->dsb->patt_val[i], - drvdata->base + TPDM_DSB_TPR(i)); - writel_relaxed(drvdata->dsb->patt_mask[i], - drvdata->base + TPDM_DSB_TPMR(i)); - writel_relaxed(drvdata->dsb->trig_patt[i], - drvdata->base + TPDM_DSB_XPR(i)); - writel_relaxed(drvdata->dsb->trig_patt_mask[i], - drvdata->base + TPDM_DSB_XPMR(i)); - } - - set_dsb_tier(drvdata); + if (tpdm_has_dsb_dataset(drvdata)) { + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl[i], + drvdata->base + TPDM_DSB_EDCR(i)); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], + drvdata->base + TPDM_DSB_EDCMR(i)); + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->patt_val[i], + drvdata->base + TPDM_DSB_TPR(i)); + writel_relaxed(drvdata->dsb->patt_mask[i], + drvdata->base + TPDM_DSB_TPMR(i)); + writel_relaxed(drvdata->dsb->trig_patt[i], + drvdata->base + TPDM_DSB_XPR(i)); + writel_relaxed(drvdata->dsb->trig_patt_mask[i], + drvdata->base + TPDM_DSB_XPMR(i)); + } - set_dsb_msr(drvdata); + set_dsb_tier(drvdata); + set_dsb_msr(drvdata); - val = readl_relaxed(drvdata->base + TPDM_DSB_CR); - /* Set the mode of DSB dataset */ - set_dsb_mode(drvdata, &val); - /* Set trigger type */ - if (drvdata->dsb->trig_type) - val |= TPDM_DSB_CR_TRIG_TYPE; - else - val &= ~TPDM_DSB_CR_TRIG_TYPE; - /* Set the enable bit of DSB control register to 1 */ - val |= TPDM_DSB_CR_ENA; - writel_relaxed(val, drvdata->base + TPDM_DSB_CR); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set the mode of DSB dataset */ + set_dsb_mode(drvdata, &val); + /* Set trigger type */ + if (drvdata->dsb->trig_type) + val |= TPDM_DSB_CR_TRIG_TYPE; + else + val &= ~TPDM_DSB_CR_TRIG_TYPE; + /* Set the enable bit of DSB control register to 1 */ + val |= TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); + } } /* @@ -278,8 +274,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - if (tpdm_has_dsb_dataset(drvdata)) - tpdm_enable_dsb(drvdata); + tpdm_enable_dsb(drvdata); CS_LOCK(drvdata->base); } @@ -307,10 +302,12 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) { u32 val; - /* Set the enable bit of DSB control register to 0 */ - val = readl_relaxed(drvdata->base + TPDM_DSB_CR); - val &= ~TPDM_DSB_CR_ENA; - writel_relaxed(val, drvdata->base + TPDM_DSB_CR); + if (tpdm_has_dsb_dataset(drvdata)) { + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val &= ~TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); + } } /* TPDM disable operations */ @@ -318,8 +315,7 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - if (tpdm_has_dsb_dataset(drvdata)) - tpdm_disable_dsb(drvdata); + tpdm_disable_dsb(drvdata); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4115b2a17b8d..ddaf333fa1c2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -220,4 +220,8 @@ struct tpdm_dataset_attribute { u32 idx; }; +static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_DSB); +} #endif /* _CORESIGHT_CORESIGHT_TPDM_H */