| Message ID | 1705634583-17631-4-git-send-email-quic_taozha@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,01/10] coresight-tpdm: Optimize the store function of tpdm simple dataset | expand |
On 19/01/2024 04:22, Tao Zhang wrote: > Add property "qcom,cmb-elem-size" to support CMB(Continuous > Multi-Bit) element for TPDM. The associated aggregator will read > this size before it is enabled. CMB element size currently only > supports 32-bit and 64-bit. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> > --- > .../bindings/arm/qcom,coresight-tpdm.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index 61ddc3b5b247..507a5f887097 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -52,6 +52,15 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint8 > enum: [32, 64] > > + qcom,cmb-element-size: > + description: > + Specifies the CMB(Continuous Multi-Bit) element size supported by > + the monitor. The associated aggregator will read this size before it > + is enabled. CMB element size currently only supports 8-bit, 32-bit > + and 64-bit. > + $ref: /schemas/types.yaml#/definitions/uint8 > + enum: [8, 32, 64] Is this in bits? If so, then qcom,cmb-element-bits or something similar. I don't quite get what is "an element" here, but I assume you do, so you will come with reasonable name. https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/property-units.yaml > + > qcom,dsb-msrs-num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -110,4 +119,22 @@ examples: > }; > }; > > + tpdm@6c29000 { You should explain why you need new example, so reviewers will not have to go back to previous discussions to ask the same question over and over again. > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x06c29000 0x1000>; > + > + qcom,cmb-element-size = /bits/ 8 <64>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + tpdm_ipcc_out_funnel_center: endpoint { > + remote-endpoint = > + <&funnel_center_in_tpdm_ipcc>; Drop unneeded wrapping / line break. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b247..507a5f887097 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-size: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 8-bit, 32-bit + and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -110,4 +119,22 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + + qcom,cmb-element-size = /bits/ 8 <64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = + <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ...