| Message ID | 1719309.HLoKcrQoNG@diego (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 5, 2014 at 2:00 PM, Heiko Stübner <heiko@sntech.de> wrote: > Introduce the grf syscon and convert the pinctrl drivers for rk3066 and rk3188 > to use it, instead of mapping the grf registers themselfs. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > Tested-by: Max Schwarz <max.schwarz@online.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Please funnel this through the ARM SoC tree with the rest of the Rockchip changes for v3.16. (I'll take patches 1-7.) Yours, Linus Walleij
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4d4dfbb..048c5de 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -79,7 +79,7 @@ pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; - reg = <0x20008000 0x150>; + rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <1>; ranges; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ed9a70a..a494fb0 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -75,17 +75,16 @@ pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; - reg = <0x20008000 0xa0>, - <0x20008164 0x1a0>; - reg-names = "base", "pull"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; #size-cells = <1>; ranges; gpio0: gpio0@0x2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>, - <0x20004064 0x8>; + reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_gates8 9>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 26e5a96..2adf1cc9e 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -31,11 +31,16 @@ reg = <0x1013c000 0x100>; }; - pmu@20004000 { - compatible = "rockchip,rk3066-pmu"; + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; reg = <0x20004000 0x100>; }; + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + gic: interrupt-controller@1013d000 { compatible = "arm,cortex-a9-gic"; interrupt-controller;