@@ -114,8 +114,8 @@ static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
static const struct clk_parent_data imx8qm_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
- { .fw_name = "acm_aud_clk0_sel" },
- { .fw_name = "acm_aud_clk1_sel" },
+ { .fw_name = "acm_aud_clk0_sel", .name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel", .name = "acm_aud_clk1_sel" },
};
static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
@@ -179,8 +179,8 @@ static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
static const struct clk_parent_data imx8qxp_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
- { .fw_name = "acm_aud_clk0_sel" },
- { .fw_name = "acm_aud_clk1_sel" },
+ { .fw_name = "acm_aud_clk0_sel", .name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel", .name = "acm_aud_clk1_sel" },
};
static struct clk_imx8_acm_sel imx8qxp_sels[] = {
@@ -231,8 +231,8 @@ static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
static const struct clk_parent_data imx8dxl_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
- { .fw_name = "acm_aud_clk0_sel" },
- { .fw_name = "acm_aud_clk1_sel" },
+ { .fw_name = "acm_aud_clk0_sel", .name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel", .name = "acm_aud_clk1_sel" },
};
static struct clk_imx8_acm_sel imx8dxl_sels[] = {
"acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, they need to have the global name. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- drivers/clk/imx/clk-imx8-acm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)