| Message ID | 1923946.Jvi0TDUXFC@wasted.cogentembedded.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Jun 01, 2016 at 01:32:35AM +0300, Sergei Shtylyov wrote: > Add the initial device tree for the R8A7792 SoC based Blanche board. > The board has 2 debug serial ports: SCIF0 and SCIF3; include support for > them, so that the serial console can work. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> At this time I do not have access to documentation or hardware for this board. So I am relying on you to test this and make sure it complies with the spec. What you have looks reasonable to me: Acked-by: Simon Horman <horms+renesas@verge.net.au>
On Wed, Jun 1, 2016 at 12:32 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the R8A7792 SoC based Blanche board. > The board has 2 debug serial ports: SCIF0 and SCIF3; include support for > them, so that the serial console can work. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 06/01/2016 04:21 AM, Simon Horman wrote: >> Add the initial device tree for the R8A7792 SoC based Blanche board. >> The board has 2 debug serial ports: SCIF0 and SCIF3; include support for >> them, so that the serial console can work. >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > At this time I do not have access to documentation or hardware for this > board. So I am relying on you to test this and make sure it complies > with the spec. Don't worry, the patches have been tested on the real hardware. > What you have looks reasonable to me: > > Acked-by: Simon Horman <horms+renesas@verge.net.au> Thank you. :-) MBR, Sergei
Index: renesas/arch/arm/boot/dts/Makefile =================================================================== --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7790-lager.dtb \ r8a7791-koelsch.dtb \ r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ r8a7793-gose.dtb \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Source for the Blanche board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7792.dtsi" + +/ { + model = "Blanche"; + compatible = "renesas,blanche", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + serial1 = &scif3; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; + +&scif3 { + status = "okay"; +};
Add the initial device tree for the R8A7792 SoC based Blanche board. The board has 2 debug serial ports: SCIF0 and SCIF3; include support for them, so that the serial console can work. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7792-blanche.dts | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)