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Wed, 24 Jun 2020 10:48:02 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Rob Herring , Michael Turquette , Philipp Zabel Subject: [PATCH v2 2/6] dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC Date: Wed, 24 Jun 2020 20:47:53 +0300 Message-Id: <1998440a1debe07f838899ccbb15c72518b6b94f.1592941257.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:543 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the missing APB, DMAC and GPIO clock bindings constants for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea --- include/dt-bindings/clock/actions,s500-cmu.h | 77 ++++++++++---------- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h index 030981cd2d56..a391d1651257 100644 --- a/include/dt-bindings/clock/actions,s500-cmu.h +++ b/include/dt-bindings/clock/actions,s500-cmu.h @@ -33,45 +33,48 @@ #define CLK_BISP 15 #define CLK_VCE 16 #define CLK_VDE 17 +#define CLK_APB 18 +#define CLK_DMAC 19 /* peripheral device clock */ -#define CLK_TIMER 18 -#define CLK_I2C0 19 -#define CLK_I2C1 20 -#define CLK_I2C2 21 -#define CLK_I2C3 22 -#define CLK_PWM0 23 -#define CLK_PWM1 24 -#define CLK_PWM2 25 -#define CLK_PWM3 26 -#define CLK_PWM4 27 -#define CLK_PWM5 28 -#define CLK_SD0 29 -#define CLK_SD1 30 -#define CLK_SD2 31 -#define CLK_SENSOR0 32 -#define CLK_SENSOR1 33 -#define CLK_SPI0 34 -#define CLK_SPI1 35 -#define CLK_SPI2 36 -#define CLK_SPI3 37 -#define CLK_UART0 38 -#define CLK_UART1 39 -#define CLK_UART2 40 -#define CLK_UART3 41 -#define CLK_UART4 42 -#define CLK_UART5 43 -#define CLK_UART6 44 -#define CLK_DE1 45 -#define CLK_DE2 46 -#define CLK_I2SRX 47 -#define CLK_I2STX 48 -#define CLK_HDMI_AUDIO 49 -#define CLK_HDMI 50 -#define CLK_SPDIF 51 -#define CLK_NAND 52 -#define CLK_ECC 53 -#define CLK_RMII_REF 54 +#define CLK_GPIO 20 +#define CLK_TIMER 21 +#define CLK_I2C0 22 +#define CLK_I2C1 23 +#define CLK_I2C2 24 +#define CLK_I2C3 25 +#define CLK_PWM0 26 +#define CLK_PWM1 27 +#define CLK_PWM2 28 +#define CLK_PWM3 29 +#define CLK_PWM4 30 +#define CLK_PWM5 31 +#define CLK_SD0 32 +#define CLK_SD1 33 +#define CLK_SD2 34 +#define CLK_SENSOR0 35 +#define CLK_SENSOR1 36 +#define CLK_SPI0 37 +#define CLK_SPI1 38 +#define CLK_SPI2 39 +#define CLK_SPI3 40 +#define CLK_UART0 41 +#define CLK_UART1 42 +#define CLK_UART2 43 +#define CLK_UART3 44 +#define CLK_UART4 45 +#define CLK_UART5 46 +#define CLK_UART6 47 +#define CLK_DE1 48 +#define CLK_DE2 49 +#define CLK_I2SRX 50 +#define CLK_I2STX 51 +#define CLK_HDMI_AUDIO 52 +#define CLK_HDMI 53 +#define CLK_SPDIF 54 +#define CLK_NAND 55 +#define CLK_ECC 56 +#define CLK_RMII_REF 57 #define CLK_NR_CLKS (CLK_RMII_REF + 1)