From patchwork Thu Apr 30 12:08:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 6302471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0703BEEE1 for ; Thu, 30 Apr 2015 12:11:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CC4F201FA for ; Thu, 30 Apr 2015 12:11:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E56C2018E for ; Thu, 30 Apr 2015 12:11:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YnnHP-00065x-61; Thu, 30 Apr 2015 12:09:23 +0000 Received: from mail-pd0-f181.google.com ([209.85.192.181]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YnnGl-0005hN-2I for linux-arm-kernel@lists.infradead.org; Thu, 30 Apr 2015 12:08:44 +0000 Received: by pdbqa5 with SMTP id qa5so58857975pdb.1 for ; Thu, 30 Apr 2015 05:08:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Jgit3wh67te5XKQnQVi7w5M/oT1tsmeFNK39NDxpq+I=; b=fKV7v92wVwQrF8/hZJLzHgIQleso8H/74/7omX0tZVoqntbJ0W1CXo9XYrkDh9h7az PyXdaQUYgaS4ZqhZQONEGyN1b+Hl9aIMKVhU+/AA52bEA8CdvrqyPeRcfaG3URCei9Q0 ep0z3ps5wNZdgzFvxjZzD2KvTDAtuGPqgkePKfbxtBdonUJDX1Jt1oimWtrwULSw36L/ FvLiR/4BwMFLVIt9hrIx7OOeSYJA2y109bVMaRaFf7QrrN14ftU8XgF4I0FUjQcvNU8k 7Mp5or7JmDClq462RxThH8lto6WJzWTYjCfBEUkEqYYSjoNr1M6mtMnMhqw+SeeVRQT2 BIMg== X-Gm-Message-State: ALoCoQlo406zhkfsLsUbJvZ0zQ6ovRmqZvQMBm0WM97v2S/t3tdKZao/mRUcQV58/SzZ1tdOy0Xc X-Received: by 10.66.55.98 with SMTP id r2mr7782300pap.22.1430395701603; Thu, 30 Apr 2015 05:08:21 -0700 (PDT) Received: from localhost ([122.178.211.250]) by mx.google.com with ESMTPSA id gl2sm2050170pbc.52.2015.04.30.05.08.20 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 30 Apr 2015 05:08:20 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , rob.herring@linaro.org, arnd.bergmann@linaro.org, nm@ti.com, broonie@kernel.org, mike.turquette@linaro.org, sboyd@codeaurora.org Subject: [PATCH V4 3/3] OPP: Add 'opp-next' in operating-points-v2 bindings Date: Thu, 30 Apr 2015 17:38:01 +0530 Message-Id: <1ee98ae5b45083e681c7f530e0ae9195e5636119.1430394884.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.3.0.rc0.44.ga94655d In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150430_050843_247382_A3D6B910 X-CRM114-Status: UNSURE ( 8.79 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.3 (/) Cc: thomas.petazzoni@free-electrons.com, devicetree@vger.kernel.org, kesavan.abhilash@gmail.com, linaro-kernel@lists.linaro.org, ta.omasab@gmail.com, linux-pm@vger.kernel.org, viswanath.puttagunta@linaro.org, Viresh Kumar , santosh.shilimkar@oracle.com, olof@lixom.net, khilman@linaro.org, Sudeep.Holla@arm.com, grant.likely@linaro.org, linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Many platforms require to switch to a intermediate frequency before switching to a final frequency. Or they can switch to only particular OPPs from any OPP. For these add another property in OPP-v2, 'opp-next'. Refer to the bindings for more details. Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/power/opp.txt | 130 ++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 07959903ec32..c96dc77121b7 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -72,6 +72,9 @@ properties. - clock-latency-ns: Specifies the maximum possible transition latency (in nanoseconds) for switching to this OPP from any other OPP. +- opp-next: It contains a list of phandles to other OPPs, to which we can switch + directly from this OPP (Explained later with examples). Missing property means + no restriction on switching to other OPPs. - turbo-mode: Marks the OPP to be used only for turbo modes. - status: Marks the node enabled/disabled. @@ -363,6 +366,133 @@ Example 4: Handling multiple regulators }; }; +Example 5: How to use "opp-next" property ? + +1.) Switch to a intermediate OPP (entry00) before switching to any other OPP. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + opp_next: entry00 { + opp-khz = <500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + /* Can switch to any OPP from here */ + }; + entry01 { + opp-khz = <600000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry02 { + opp-khz = <900000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry03 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry04 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + opp-next = <&opp_next>; + }; + entry05 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + opp-next = <&opp_next>; + turbo-mode; + }; + }; +}; + +2.) Can only switch to the next or previous OPP directly. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + opp_next0: entry00 { + opp-khz = <500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next1>; + }; + opp_next1: entry01 { + opp-khz = <600000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next0>, <&opp_next2>; + }; + opp_next2: entry02 { + opp-khz = <900000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next1>, <&opp_next3>; + }; + opp_next3: entry03 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next2>, <&opp_next4>; + }; + opp_next4: entry04 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + opp-next = <&opp_next3>, <&opp_next5>; + }; + opp_next5: entry05 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + opp-next = <&opp_next4>; + turbo-mode; + }; + }; +}; + + Deprecated Bindings -------------------