From patchwork Mon May 22 14:59:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 13250730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46939C7EE2D for ; Mon, 22 May 2023 15:01:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MHmvpfN60dKDsNU5CEY2xt/MagpEb4jMn3DYzOxyQ00=; b=vsq135uS6JYlb8 XxZ69UN9qqUXyQWQJvW2pHPh+zGSSpg0leuK2NscZXIRQfIyy/4QGogDdXEMtd8ZydmfBjCX6JEts hCYWYcTKr/+U5VW6rJGCg5uGe0vuomaWJqrWC0PlhPD6w7bqMvfh5YQikRjMsZDVRH1fRal4zNSVO bS3BUGJLgIECLAdEguAXFzjjeTGAl9yDYbBkRpDm76wjBi12Wq8189CWlZr4wGPvqHf2uY9zM4xDJ ZlsBEvKofUZZ9osyoGWoKrtLfPTiZNzWs0Hg07UilrXCckyV5K8B/G9QlUhKxO9EmkhsYI4vBMPDy JfDeFQPAMEUv2sDouliQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q171i-006vZ2-38; Mon, 22 May 2023 15:00:46 +0000 Received: from mail-mw2nam12on20618.outbound.protection.outlook.com ([2a01:111:f400:fe5a::618] helo=NAM12-MW2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q171e-006vWP-1C for linux-arm-kernel@lists.infradead.org; Mon, 22 May 2023 15:00:44 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=d8gYYKSixPE1iYmdl3RFTFO40yJObEFgY+vEpkby5qwMs87MZr9/fLhZoDkImhFpt5jFHOuAEJ1zMqr6YwBMwvuy0WI00KJ1g5itMw6xBTGMhdZZDN8pmwHULjG/N4q9oYnlN+IrRRqrBbJSBlugGK1+VxJHsygrBokBpKZJECdtvgzc031a+gkgf9QrhVI3Rjhd4LrNm4n1tQ8PfoDJCU9ycWSebXpLcy97GMRBHjP5CE976yDSAQVCt7oRhIXhNGyM8jGoAYY5sIjl+V3vlZ9geGC398p2Ruu3t6Mx7BGwEm5jPArO5e3HQD7P2l+EMmqJLWuC165F5PvSmA1t3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HKaDwKWgGj34kfV7+Xy4ofeKe4phzNS1X5wo8c80Ag4=; b=MudnKY4L8WPyCcE5sx3tQdEVsqqZMf5dmkRAURTrTbkfpKNpH3rlNXdSIRqPNNMpe2wpbuP3SMb3AICVvVeAu2SoLMkVFasSZOFjAul4kdL/f8uUj26KB6YyQ99qb3Szrr/viTltP76miwFoqFNlY37gwF2Z45JxfWI6GcZyiT55gXhzuEGXLw3NiyokTfEFB4swMzvEblbTPCGg/kA2MG9QKE9PbmrR+UzNOyKcF6tP2mzeQ4WGVMTYagpHQc4nczsPUsc8fZVARKRnZEEqAxDphBixKAQOSFhCIUsQvN+m1kLNJTAz1OlDoi03UmCVyq8tqfXZZDD21Kh0v8Xm2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HKaDwKWgGj34kfV7+Xy4ofeKe4phzNS1X5wo8c80Ag4=; b=Xi4fag9hCpdCtZLXAfY70/1f/QLcumc77rSMR89VXsDo6yCNgOW1TvTlU/aCBOehErnXaLIBVLGWCgrjGGXTeWgTfs/segKgMk3i3yOeZesgIl2Ost/+rWYcWxbbqVpQaDg4YcJUhhb+fTexPFZc1tkyZi1tM4WtMqmyJY52qM0= Received: from DM6PR01CA0022.prod.exchangelabs.com (2603:10b6:5:296::27) by PH7PR12MB7794.namprd12.prod.outlook.com (2603:10b6:510:276::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6411.25; Mon, 22 May 2023 15:00:37 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:5:296:cafe::3e) by DM6PR01CA0022.outlook.office365.com (2603:10b6:5:296::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6411.28 via Frontend Transport; Mon, 22 May 2023 15:00:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.28 via Frontend Transport; Mon, 22 May 2023 15:00:37 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 22 May 2023 10:00:29 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Ashok Reddy Soma , Conor Dooley , "Krzysztof Kozlowski" , Laurent Pinchart , Parth Gajjar , "Rob Herring" , Srinivas Neeli , Vishal Sagar , , Subject: [PATCH v2 3/6] arm64: zynqmp: Set qspi tx-buswidth to 4 Date: Mon, 22 May 2023 16:59:50 +0200 Message-ID: <1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7340; i=michal.simek@amd.com; h=from:subject:message-id; bh=Gl+tyTMoFNKlU3UiJWQaU4vwmFqPHKaLGnnaY76ai98=; b=owGbwMvMwCR4yjP1tKYXjyLjabUkhpTs5rj5jhabvv30DDy29aHh04Dgy7ysuRe4c2eXLz2+7 YImR1RjRywLgyATg6yYIou0zZUzeytnTBG+eFgOZg4rE8gQBi5OAZjIC2uG+Y5ngnYqnfgQMVk3 UrncUL2lfsvKNwwLpjst+tG9SSJ1was7bcufP+t3Zr3ZDgA= X-Developer-Key: i=michal.simek@amd.com; a=openpgp; fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT022:EE_|PH7PR12MB7794:EE_ X-MS-Office365-Filtering-Correlation-Id: 79c799cc-27f3-4ab5-691d-08db5ad54d6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PnUbs3+f+T2KgaQlrhZS95pc6jCCuAl8XckWr8+aaZ24HdaarJIH16lH9kCarykdaslZCL65JGe7M9CCALA021d7tI9/18Gnz7N/2LRrEAtEtsk2T2e/ud8eQebdUJM2lT9ma7tL2HOER5BzlTUbxrzx1bjrxdUkMnCezzafOijXh/Vtmev2q4nTY1EEOqSxWc9keRRVOt0PWds+wFiaR9gz2UPklPEJmWw/GFAkkDZYeIZx98qxSVIbgOjiPuDMVp9UBHPG+PtKMjJ6kRwchqy4pbAqXn4blJlWNC8XrOgnme+WC23f+SXmJ14a88QFPtZK/7oZMNuXZyfuyx2lvn9ZuKDWXBfXrTMxWHzQj5x/DhQ96bUE7IXuU9gdGed5PyT9asDrV/g13VtSLknDIUqKU3XCYHWW2+AoWBB4kJ6tWmy5lQsgxI0Emp3b87sEQsqctbpkVbidGY8roUAWhAPwe9TTHo2ZgclNzudUrpyP10DaHrJrNmKLai5OGKv0dZ4cOrZog32e62iBkEhiDiP7r80/iWxG6ihPeU8bdTvbHksVokAbiYdih5pM9a0gLbC9MZlX5pbneRV8e2YkKROiuyH6jTgA9Az5dxaHQ4f6vOgc7jL4YLM6TbnbvmOpO7mEeQHJraOfGO0unCmBw78CmqDt9pHRq1x8A7tQu8XaD0nVlXxr1WXadNDeWekJxs5FvGBAv5Obavs2DD7vtbxsztjtk03AobYAmdy52FjidnFx2J/1SCVPIKJln43oZ+IWjNgkMmb8M/q86+5Q3OxS7N6ZGB8taKzHYE1Y8qg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(8676002)(8936002)(47076005)(5660300002)(7416002)(44832011)(83380400001)(36860700001)(82310400005)(16526019)(186003)(336012)(26005)(426003)(2616005)(81166007)(86362001)(356005)(82740400003)(40460700003)(41300700001)(40480700001)(70206006)(6666004)(478600001)(70586007)(4326008)(316002)(110136005)(36756003)(54906003)(2906002)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 15:00:37.5629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79c799cc-27f3-4ab5-691d-08db5ad54d6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7794 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230522_080042_414633_C870AE0B X-CRM114-Status: GOOD ( 14.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Amit Kumar Mahapatra All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek --- Changes in v2: - Update commit message to skip spi-nor part - reported by Laurent arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index c1ab1ab690df..84e18fdce775 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -124,7 +124,7 @@ spi_flash: flash@0 { /* MT25QU512A */ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 48d6a7202406..04079d1704f1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -44,7 +44,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index e80484f9b137..3dec57cf18be 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -45,7 +45,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index af3331c133ad..d9d1de5f313c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -355,7 +355,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05be71eab722..6636e76545a5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -173,7 +173,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index a074d8e2b86d..8767f147cbe3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -957,7 +957,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 91c9b77f6b1f..e185709c0d84 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -444,7 +444,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 954044d9899f..7fceebd1815c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -456,7 +456,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index ab5e34b43642..27b2416cb6d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -964,7 +964,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index f31365a14f73..6224365826d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -794,7 +794,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index e615286b8eff..c406017b0348 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -47,7 +47,7 @@ &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; };