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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r1t1+K70MuQ6CIfy7Wgp1L7Kl8mx3XOTA4Vtxtq+eOs=; b=sQuSNG1A1OpDVTkJl8oLdw8Nt1A+zzshEwHcvkVTPvwjzEwkDGawOux/lOimVN9xO9 XKu3OsgiJKIzMv7qeSgixLEgKKTlQkUJ9vhFWRCAbymA6xhIrNTqe1dy3qw5VTXD/Pxe HkLuaABAx2ppBdVFS/BDEzE6T8MP4c08CNULQTIx2AsaTzdhD/DmfNQ+acLg5cUm610T vjGPa7c8cA+lX8X5JR4oS7T8moEPogeIBDDQiBEF180VafugiW0Px65Q7gqyVzSXoazm M4X7hvT8+G4VT32NbddFM12NXAeLQa2bvIb1WF0K3oTzmkFg15HZ6ucKp3ENIDcgfDgp kDAQ== X-Gm-Message-State: AGRZ1gIn7NHB/y22ZCFtI1AuIW2vFYQ/b5rNyhhkyXUne7YG0iIYyrYD lD6U3XmZc8NaGN4hhwHVmIY= X-Google-Smtp-Source: AJdET5c4Zqajrupn6z1eF0bRHaiePEngnhFgTPALCDwKdmY/qNKgrMSteBc1bwjNYy4fDw/HqKSE3w== X-Received: by 2002:a1c:b58b:: with SMTP id e133mr20180076wmf.0.1543131837991; Sat, 24 Nov 2018 23:43:57 -0800 (PST) Received: from localhost.localdomain ([185.219.177.224]) by smtp.gmail.com with ESMTPSA id 6-v6sm12296780wmg.19.2018.11.24.23.43.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 24 Nov 2018 23:43:57 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [RFC PATCH v4 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Date: Sun, 25 Nov 2018 10:43:10 +0300 Message-Id: <1f3cce09623052eaa90093f13ea9d13047a2b250.1543131714.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181124_234409_552925_A724303A X-CRM114-Status: GOOD ( 16.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mesih Kilinc , Julian Calaby , Linus Walleij , Daniel Lezcano , Russell King , Marc Zyngier , Chen-Yu Tsai , Rob Herring , Maxime Ripard , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 47 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 507f4e3..fb78d66 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -32,6 +32,8 @@ #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 #define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 struct sun4i_irq_chip_data { void __iomem *irq_base; @@ -105,15 +107,6 @@ static const struct irq_domain_ops sun4i_irq_ops = { static int __init sun4i_of_init(struct device_node *node, struct device_node *parent) { - irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); - if (!irq_ic_data) { - pr_err("kzalloc failed!\n"); - return -ENOMEM; - } - - irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; - irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; - irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", @@ -149,7 +142,41 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", + suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) {