From patchwork Wed May 7 21:14:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 4132041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 752799F1E1 for ; Wed, 7 May 2014 21:16:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7367820222 for ; Wed, 7 May 2014 21:16:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67F76201FB for ; Wed, 7 May 2014 21:16:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi9A7-00086F-0D; Wed, 07 May 2014 21:13:59 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi9A4-0007sX-FX for linux-arm-kernel@lists.infradead.org; Wed, 07 May 2014 21:13:57 +0000 Received: from 146-52-69-41-dynip.superkabel.de ([146.52.69.41] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1Wi99h-00037R-4Y; Wed, 07 May 2014 23:13:33 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Mike Turquette Subject: [PATCH v2 06/11] dt-bindings: add documentation for rk3188 clock and reset unit Date: Wed, 07 May 2014 23:14:10 +0200 Message-ID: <2003795.Fases3iJaR@diego> User-Agent: KMail/4.11.5 (Linux/3.13-1-amd64; KDE/4.11.3; x86_64; ; ) In-Reply-To: <3477211.Gkyeur83TV@diego> References: <3477211.Gkyeur83TV@diego> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140507_141356_682774_77B393B0 X-CRM114-Status: GOOD ( 12.37 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, arm@kernel.org, Pawel Moll , Ian Campbell , Rob Herring , Kumar Gala , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This add bindings documentation for the clock and reset unit found on rk3188 SoCs from Rockchip. Signed-off-by: Heiko Stuebner --- .../bindings/clock/rockchip,rk3188-cru.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt new file mode 100644 index 0000000..8165c0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt @@ -0,0 +1,74 @@ +* Rockchip RK3188 Clock and Reset Unit + +The RK3188 clock controller generates and supplies clock to various controllers +within the SoC and also implements a reset controller for SoC peripherals. +There exist two variants of the rk3188 SoC, the rk3188 and rk3188a, with +slight differences in the pll handling. + +Required Properties: + +- compatible: should be "rockchip,rk3188-cru" or "rockchip,rk3188a-cru" +- reg: physical base address of the controller and length of memory mapped + region. The first element should be the cru register space and the second + element should be the address of the GRF_SOC_STATUS register providing the + pll lock status. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +- rockchip,armclk-divider-table: when the frequency of the APLL is changed + some core divider clocks also need to be updated. These divider clocks have + SoC specific divider clock output requirements for a specific APLL clock + speeds. When APLL clock rate is changed, these divider clocks are + reprogrammed with pre-determined values in order to maintain the SoC + specific divider clock outputs. This property lists the divider values + for these clocks for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + defined as + + cell #1: arm clock parent frequency + cell #2 ~ cell 3#: value of clock divider of core_peri and aclk_core. + +- #rockchip,armclk-cells: defines the number of cells in + rockchip,armclk-divider-table property. The value of this property depends on + the SoC type. For RK3188 SoCs it should be 3. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in dt-bindings/clock/rk3188-cru.h header and can be used +in device tree sources. + +External clocks: + +The basic input clock is generated outside the SoC. It is expected that it is +defined using standard clock bindings with a clock-output-name of "xin24m". + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>, + <0x200080ac 0x4>; + + #clock-cells = <1>; + + #rockchip,armclk-cells = <3>; + rockchip,armclk-divider-table = <1608000 2 3>, + <1416000 2 3>, + <1200000 2 3>, + <1008000 2 3>, + < 816000 2 3>, + < 504000 1 3>, + < 312000 0 1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + };