From patchwork Sun Jul 1 18:41:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Machek X-Patchwork-Id: 1145061 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id AA4E440ABE for ; Sun, 1 Jul 2012 18:46:23 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SlP5e-0002XH-Hj; Sun, 01 Jul 2012 18:41:46 +0000 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SlP5V-0002X3-BV for linux-arm-kernel@lists.infradead.org; Sun, 01 Jul 2012 18:41:43 +0000 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id 09230F0818; Sun, 1 Jul 2012 20:41:36 +0200 (CEST) Date: Sun, 1 Jul 2012 20:41:10 +0200 From: Pavel Machek To: Arnd Bergmann Subject: Re: [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. Message-ID: <20120701184110.GA30680@elf.ucw.cz> References: <1340805007-3313-1-git-send-email-dinguyen@altera.com> <20120627180516.GA17393@elf.ucw.cz> <20120627204018.0bfef362@skate> <201206302104.37937.arnd@arndb.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <201206302104.37937.arnd@arndb.de> X-Warning: Reading this can be dangerous to your mental health. User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [195.113.26.193 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Thomas Petazzoni , linux@arm.linux.org.uk, wd@denx.de, cytan@altera.com, linux-arm-kernel@lists.infradead.org, dinguyen@altera.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Sat 2012-06-30 21:04:37, Arnd Bergmann wrote: > On Wednesday 27 June 2012, Thomas Petazzoni wrote: > > > > > +#define NR_IRQS 512 > > > > > > > > You should be looking at using SPARSE_IRQ to avoid having a maximum > > > > number of irqs. See for example mach-highbank/. > > > > > > Is maximum number of interrupts a problem? 512 does not seem > > > excessive. > > > > Regardless of the value of NR_IRQS, there is apparently a trend to use > > SPARSE_IRQ anyway. However, I am not at the best place to explain why > > SPARSE_IRQ is now considered the right thing to use. > > The main reason for me is to get rid of a hardcoded NR_IRQS constant, > whihc is a blocker for multiplatform kernels. New platforms should > do all they can to allow being built together with other platforms > in the same kernel. While we're not there yet, doing sparse irq > is an important step in the right direction and should not be hard > to do for new code. Something as easy as this? But it does not seem to boot here :-(. Pavel diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b1578e1..d203253 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -263,6 +263,7 @@ config ARCH_SOCFPGA select GPIO_PL061 if GPIOLIB select NEED_MACH_MEMORY_H select USE_OF + select SPARSE_IRQ help This enables support for Altera SOCFPGA Cyclone V platform diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h index da50124..565ca59 100644 --- a/arch/arm/mach-socfpga/include/mach/irqs.h +++ b/arch/arm/mach-socfpga/include/mach/irqs.h @@ -27,8 +27,6 @@ #define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ -#define NR_IRQS 512 - #define MAX_GIC_NR 1 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index f6498cc..674bac3 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,11 @@ static void socfpga_cyclone5_restart(char mode, const char *cmd) static void __init socfpga_cyclone5_init(void) { + int i; + for (i = 0; i < 512; i++) { + dynamic_irq_init(i); + } + #ifdef CONFIG_CACHE_L2X0 /* 8-way, 64K/way, evmon/parity/share */ l2x0_of_init(0x00760000, 0xfe000fff);