From patchwork Thu Aug 9 12:01:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 1300181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 2E901DFF7B for ; Thu, 9 Aug 2012 12:05:08 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SzRQb-0004WK-Ke; Thu, 09 Aug 2012 12:01:25 +0000 Received: from ch1ehsobe005.messaging.microsoft.com ([216.32.181.185] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SzRQY-0004W6-Sd for linux-arm-kernel@lists.infradead.org; Thu, 09 Aug 2012 12:01:23 +0000 Received: from mail147-ch1-R.bigfish.com (10.43.68.229) by CH1EHSOBE006.bigfish.com (10.43.70.56) with Microsoft SMTP Server id 14.1.225.23; Thu, 9 Aug 2012 12:01:20 +0000 Received: from mail147-ch1 (localhost [127.0.0.1]) by mail147-ch1-R.bigfish.com (Postfix) with ESMTP id 091203601EF; Thu, 9 Aug 2012 12:01:20 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(zcb8kz98dI1432Izz1202hzzz2dh87h2a8h668h839h944hd25he96hf0ah107ah) X-FB-DOMAIN-IP-MATCH: fail Received: from mail147-ch1 (localhost.localdomain [127.0.0.1]) by mail147-ch1 (MessageSwitch) id 1344513676797226_25206; Thu, 9 Aug 2012 12:01:16 +0000 (UTC) Received: from CH1EHSMHS009.bigfish.com (snatpool3.int.messaging.microsoft.com [10.43.68.229]) by mail147-ch1.bigfish.com (Postfix) with ESMTP id B6D0D2C004B; Thu, 9 Aug 2012 12:01:16 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS009.bigfish.com (10.43.70.9) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 9 Aug 2012 12:01:16 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.298.5; Thu, 9 Aug 2012 07:01:15 -0500 Received: from S2101-09.ap.freescale.net ([10.192.185.57]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q79C17iw032341; Thu, 9 Aug 2012 05:01:13 -0700 Date: Thu, 9 Aug 2012 20:01:47 +0800 From: Shawn Guo To: Russell King - ARM Linux Subject: Re: imx6q restart is broken Message-ID: <20120809120144.GA19617@S2101-09.ap.freescale.net> References: <20120808101817.GA14718@S2101-09.ap.freescale.net> <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com> <20120809092021.GQ18957@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20120809092021.GQ18957@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: sigmatel.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.185 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Dirk Behme , Sascha Hauer , Hui Wang , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Thu, Aug 09, 2012 at 10:20:21AM +0100, Russell King - ARM Linux wrote: > I suspect having this dmb inside cpu_relax() is flooding the > interconnects with traffic, which then prevents other CPUs getting > a look-in (maybe there's no fairness when it comes to dmb's. > > If I'm right, you'll find is that even converting this to the ARMv7 > DMB instruction won't fix the problem. It does, however, point > towards a more serious problem - it means that any tight loop using > dmb is detremental. I have heard some people mention that even on > various ARM SMP platforms, they have see quite an amount of > interaction between the individual CPU cores, and I'm beginning > to wonder whether this is why. > > I think a useful test would be to only execute the DMB maybe once > in 50 or 100 loops - the DMB is there to work around a different > problem with the temporal locality of stores on the local CPU. So, > the only requirement is that we issue a DMB at some point while > spinning waiting for another CPU to respond to our previous writes. You got it. The following change fixed the problem for me. But I think you only meant it for testing. So how should we actually fix the problem? Regards, Shawn --8<--- linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 99afa74..1282b61 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -80,11 +80,18 @@ extern void release_thread(struct task_struct *); unsigned long get_wchan(struct task_struct *p); #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327) -#define cpu_relax() smp_mb() +#define __cpu_relax() smp_mb() #else -#define cpu_relax() barrier() +#define __cpu_relax() barrier() #endif +#define cpu_relax() \ +({ \ + static int i; \ + if (i++ % 100) \ + __cpu_relax(); \ +}) + _______________________________________________