From patchwork Sat Sep 15 15:35:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1462151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 740C8E00C3 for ; Sat, 15 Sep 2012 15:39:55 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TCuPS-0007qZ-N2; Sat, 15 Sep 2012 15:35:55 +0000 Received: from mail-qc0-f177.google.com ([209.85.216.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TCuOd-0007fd-Fn for linux-arm-kernel@lists.infradead.org; Sat, 15 Sep 2012 15:35:04 +0000 Received: by mail-qc0-f177.google.com with SMTP id u28so3767182qcs.36 for ; Sat, 15 Sep 2012 08:35:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:date:message-id:in-reply-to:references:user-agent :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=+2MuSXZ2Dpdie+CTsuFd1vc63ETOZkmx2lJhMv+nAv4=; b=dGyhjj88kzQw+xi+Rw9lPsFpmDcnvRjX1WHGlyNhbBBUG4q1smB7xj7cr6/SJVpb55 k+ITI1raUJiTAgr0ikYDQu4yCqLqzfbM8k1hqcOVezMZ56GHLs7NdBVs+Ml1xtRMd5EP yIWb5vIrYNH9btS7ol0Cb1U8XlGEKZzG1+ArOGlawBfAdLuBHkjZvCLNTnaw6ABOtyVo A4DwW3YQjHu+vvEfyoYQEs1RYiXL4iMoBHstDAzuBF2pQpstEsO0B4UEnV1wvZKJope5 kbxAps6koLb91LOVIc4Nb2STHoVJKnfsfpVG8TwoElWebglMHLLmd3FkQDqECR0nn84l gA/w== Received: by 10.224.193.193 with SMTP id dv1mr2125422qab.29.1347723303239; Sat, 15 Sep 2012 08:35:03 -0700 (PDT) Received: from [127.0.1.1] (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id bh14sm7010849qab.2.2012.09.15.08.35.02 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 15 Sep 2012 08:35:02 -0700 (PDT) Subject: [PATCH 05/15] ARM: Expose PMNC bitfields for KVM use To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu From: Christoffer Dall Date: Sat, 15 Sep 2012 11:35:02 -0400 Message-ID: <20120915153502.21241.13218.stgit@ubuntu> In-Reply-To: <20120915153359.21241.86002.stgit@ubuntu> References: <20120915153359.21241.86002.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmNM9+NTdXmJI3bprW7HhZmha+sQPNyJTUBkMaSCGSYQqa9iFqTqRoI/mvVmKGnUNNrV7OA X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Rusty Russell We want some of these for use in KVM, so pull them out of arch/arm/kernel/perf_event_v7.c into their own asm/perf_bits.h. Signed-off-by: Rusty Russell Signed-off-by: Christoffer Dall --- arch/arm/include/asm/perf_bits.h | 56 ++++++++++++++++++++++++++++++++++++++ arch/arm/kernel/perf_event_v7.c | 51 +---------------------------------- 2 files changed, 57 insertions(+), 50 deletions(-) create mode 100644 arch/arm/include/asm/perf_bits.h diff --git a/arch/arm/include/asm/perf_bits.h b/arch/arm/include/asm/perf_bits.h new file mode 100644 index 0000000..eeb266a --- /dev/null +++ b/arch/arm/include/asm/perf_bits.h @@ -0,0 +1,56 @@ +#ifndef __ARM_PERF_BITS_H__ +#define __ARM_PERF_BITS_H__ + +/* + * ARMv7 low level PMNC access + */ + +/* + * Per-CPU PMNC: config reg + */ +#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ +#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ +#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ +#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ +#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ +#define ARMV7_PMNC_N_MASK 0x1f +#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ + +/* + * FLAG: counters overflow flag status reg + */ +#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */ +#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv2 + */ +#define ARMV7_EXCLUDE_PL1 (1 << 31) +#define ARMV7_EXCLUDE_USER (1 << 30) +#define ARMV7_INCLUDE_HYP (1 << 27) + +#ifndef __ASSEMBLY__ +static inline u32 armv7_pmnc_read(void) +{ + u32 val; + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); + return val; +} + +static inline void armv7_pmnc_write(u32 val) +{ + val &= ARMV7_PMNC_MASK; + isb(); + asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); +} +#endif + +#endif /* __ARM_PERF_BITS_H__ */ diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index f04070b..09851b3 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -17,6 +17,7 @@ */ #ifdef CONFIG_CPU_V7 +#include static struct arm_pmu armv7pmu; @@ -744,61 +745,11 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) /* - * ARMv7 low level PMNC access - */ - -/* * Perf Event to low level counters mapping */ #define ARMV7_IDX_TO_COUNTER(x) \ (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) -/* - * Per-CPU PMNC: config reg - */ -#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ -#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ -#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ -#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ -#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ -#define ARMV7_PMNC_N_MASK 0x1f -#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ - -/* - * FLAG: counters overflow flag status reg - */ -#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */ -#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv2 - */ -#define ARMV7_EXCLUDE_PL1 (1 << 31) -#define ARMV7_EXCLUDE_USER (1 << 30) -#define ARMV7_INCLUDE_HYP (1 << 27) - -static inline u32 armv7_pmnc_read(void) -{ - u32 val; - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); - return val; -} - -static inline void armv7_pmnc_write(u32 val) -{ - val &= ARMV7_PMNC_MASK; - isb(); - asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); -} - static inline int armv7_pmnc_has_overflowed(u32 pmnc) { return pmnc & ARMV7_OVERFLOWED_MASK;