From patchwork Thu Sep 27 16:15:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1515111 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id EDEB43FE1C for ; Thu, 27 Sep 2012 16:18:02 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1THGku-0007yD-QG; Thu, 27 Sep 2012 16:16:04 +0000 Received: from service87.mimecast.com ([91.220.42.44]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1THGkp-0007xz-Ss for linux-arm-kernel@lists.infradead.org; Thu, 27 Sep 2012 16:16:01 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 27 Sep 2012 17:15:56 +0100 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 27 Sep 2012 17:15:55 +0100 Date: Thu, 27 Sep 2012 17:15:52 +0100 From: Lorenzo Pieralisi To: Russell King - ARM Linux Subject: Re: [GIT PULL] ARM: cache flushing LoUIS API Message-ID: <20120927161552.GA5001@e102568-lin.cambridge.arm.com> References: <20120925125758.GA16842@e102568-lin.cambridge.arm.com> <20120927114805.GC14358@n2100.arm.linux.org.uk> MIME-Version: 1.0 In-Reply-To: <20120927114805.GC14358@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 27 Sep 2012 16:15:55.0627 (UTC) FILETIME=[5F639BB0:01CD9CCB] X-MC-Unique: 112092717155625301 Content-Disposition: inline X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [91.220.42.44 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "nicolas.pitre@linaro.org" , shawn.guo@linaro.org, "santosh.shilimkar@ti.com" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org [CC'ed Shawn to test T2 on iMX] On Thu, Sep 27, 2012 at 12:48:05PM +0100, Russell King - ARM Linux wrote: > On Tue, Sep 25, 2012 at 01:57:58PM +0100, Lorenzo Pieralisi wrote: > > Hi Russell, > > > > I know it is coming quite late in the cycle but please consider pulling > > the patch series implementing the new cache maintenance LoUIS API, since > > it provides a stepping stone to implementing power management on upcoming > > A15 and A7 based platforms, leaving functionality for earlier processor > > versions unchanged. > > > > It has been tested on: > > > > - OMAP4/5 > > # suspend/hotplug and CPU idle > > - iMX6q > > # suspend and hotplug > > - TC2 big.LITTLE testchip > > # CPU idle > > Ok, last night's PXA build regressed with this: > > arch/arm/mm/built-in.o: In function `xscale_dma_unmap_area': > cache-xsc3l2.c:(.text+0x4194): undefined reference to `xscale_80200_A0_A1_flush_kern_cache_louis' > > That's because we missed that proc-xscale.S aliases a bunch of functions to > xscale_80200_A0_A1_xxx from xscale_xxx. And looking at that, it seems that > we also .type equivalent symbols - have you tested this on T2 builds to > check whether it works correctly there? Tested T2 build on TC2 testchip and everything seems to be working fine. Santosh, Shawn, can you give T2 a go on OMAP and iMX6 please ? As for the xscale (and feroceon I think as well) regressions, I had a look and put together this patch, following the pattern in the respective .S files. It is true that we end up having a chain of equivalent symbols. Russell, Do you think it is sufficient/proper or you see other issues ? If it is ok I can fold it into the series and prepare a new pull request. Thanks a lot for your help and sorry again. Lorenzo -- >8 -- Subject: [PATCH] ARM: mm: fix cache LoUIS API for xscale and feroceon Some architectures like xscale and feroceon have cache API variants that map cache flushing functions as aliases to the base architecture. This patch adds the required aliases to complete the implementation of cache flushing LoUIS API. Signed-off-by: Lorenzo Pieralisi --- arch/arm/mm/proc-feroceon.S | 1 + arch/arm/mm/proc-xscale.S | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 85e5e3b..4106b09 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -434,6 +434,7 @@ ENDPROC(feroceon_dma_unmap_area) range_alias flush_icache_all range_alias flush_user_cache_all range_alias flush_kern_cache_all + range_alias flush_kern_cache_louis range_alias flush_user_cache_range range_alias coherent_kern_range range_alias coherent_user_range diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index b5ea31d..2551036 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -442,6 +442,7 @@ ENDPROC(xscale_dma_unmap_area) a0_alias flush_icache_all a0_alias flush_user_cache_all a0_alias flush_kern_cache_all + a0_alias flush_kern_cache_louis a0_alias flush_user_cache_range a0_alias coherent_kern_range a0_alias coherent_user_range