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[72.80.83.148]) by mx.google.com with ESMTPS id b5sm23779784qao.13.2012.10.01.02.10.21 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 01 Oct 2012 02:10:22 -0700 (PDT) Subject: [PATCH v2 03/14] ARM: Factor out cpuid implementor and part number To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu From: Christoffer Dall Date: Mon, 01 Oct 2012 05:10:20 -0400 Message-ID: <20121001091020.49198.94718.stgit@ubuntu> In-Reply-To: <20121001090945.49198.68950.stgit@ubuntu> References: <20121001090945.49198.68950.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnWkdNNRIqDixhgUJfgJJuj8dxHs7wr7JNFS1WlzS79/Od6aB66QBKW3cyhyLGcI6+oK8dk X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decoding the implementor and part number of the CPU id in the CPU ID register is needed by KVM, so we factor it out to share the code. Signed-off-by: Christoffer Dall --- arch/arm/include/asm/cputype.h | 26 ++++++++++++++++++++++++++ arch/arm/kernel/perf_event.c | 30 +++++++++++++++--------------- 2 files changed, 41 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb47d28..306fb2c 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -51,6 +51,22 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define IMPLEMENTOR_ARM 0x41 +#define IMPLEMENTOR_INTEL 0x69 + +#define PART_NUMBER_ARM1136 0xB360 +#define PART_NUMBER_ARM1156 0xB560 +#define PART_NUMBER_ARM1176 0xB760 +#define PART_NUMBER_ARM11MPCORE 0xB020 +#define PART_NUMBER_CORTEX_A8 0xC080 +#define PART_NUMBER_CORTEX_A9 0xC090 +#define PART_NUMBER_CORTEX_A5 0xC050 +#define PART_NUMBER_CORTEX_A15 0xC0F0 +#define PART_NUMBER_CORTEX_A7 0xC070 + +#define PART_NUMBER_XSCALE1 0x1 +#define PART_NUMBER_XSCALE2 0x2 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -61,6 +77,16 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return (read_cpuid_id() & 0xFFF0); +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index ab243b8..c8243c6 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -709,44 +709,44 @@ static int __init init_hw_perf_events(void) { unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == IMPLEMENTOR_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case PART_NUMBER_ARM1136: + case PART_NUMBER_ARM1156: + case PART_NUMBER_ARM1176: cpu_pmu = armv6pmu_init(); break; - case 0xB020: /* ARM11mpcore */ + case PART_NUMBER_ARM11MPCORE: cpu_pmu = armv6mpcore_pmu_init(); break; - case 0xC080: /* Cortex-A8 */ + case PART_NUMBER_CORTEX_A8: cpu_pmu = armv7_a8_pmu_init(); break; - case 0xC090: /* Cortex-A9 */ + case PART_NUMBER_CORTEX_A9: cpu_pmu = armv7_a9_pmu_init(); break; - case 0xC050: /* Cortex-A5 */ + case PART_NUMBER_CORTEX_A5: cpu_pmu = armv7_a5_pmu_init(); break; - case 0xC0F0: /* Cortex-A15 */ + case PART_NUMBER_CORTEX_A15: cpu_pmu = armv7_a15_pmu_init(); break; - case 0xC070: /* Cortex-A7 */ + case PART_NUMBER_CORTEX_A7: cpu_pmu = armv7_a7_pmu_init(); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { + } else if (implementor == IMPLEMENTOR_INTEL) { part_number = (cpuid >> 13) & 0x7; switch (part_number) { - case 1: + case PART_NUMBER_XSCALE1: cpu_pmu = xscale1pmu_init(); break; - case 2: + case PART_NUMBER_XSCALE2: cpu_pmu = xscale2pmu_init(); break; }