From patchwork Mon Oct 22 06:53:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1624271 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C7B06400E8 for ; Mon, 22 Oct 2012 07:10:53 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQC6f-0002tZ-Id; Mon, 22 Oct 2012 07:07:27 +0000 Received: from mail-vc0-f177.google.com ([209.85.220.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TQBt8-00018M-K7 for linux-arm-kernel@lists.infradead.org; Mon, 22 Oct 2012 06:53:29 +0000 Received: by mail-vc0-f177.google.com with SMTP id p16so2568870vcq.36 for ; Sun, 21 Oct 2012 23:53:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=3jUZM3uT6J/qJZY8ppj7puWJMRXb1KoG8Zz3YJt+VtU=; b=d7NeCmjwVtH6zP3AIpBiOpizVz60yH3X6z3iu8/jfhCifHJDN4A6vEPo3pg9Q2Ao+B L+D6FdgFOf+bPBFq4xJmIGsOWCx0iJFWPekTTKhfMoC/XgifCBLgxbtX0IBeWFFMNJmR ViJ3L5DHvTBZ8xCMXI8ZBcvo0xbcFNoZeY4g0E40LPELu5csy1v1y0fuwr1w/LZ35o1d Tgb1nXEveQ78QlDUm74gji5LNiuOS9Kp2MeE2Kp5LpOqIlrWNlLDdUJAMqg/ZRisrjJI +8IhqixurNAxQX/SjmK7PmAyprIgsH0GlFjF336xf7bx/OG1ZpnAGhanlskXr3kjyXSO GUqw== Received: by 10.58.155.169 with SMTP id vx9mr14287671veb.45.1350888806328; Sun, 21 Oct 2012 23:53:26 -0700 (PDT) Received: from [127.0.1.1] (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id vl8sm8969744veb.9.2012.10.21.23.53.25 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 21 Oct 2012 23:53:26 -0700 (PDT) Subject: [PATCH v3 4/5] ARM: KVM: arch_timers: Add timer world switch To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu From: Christoffer Dall Date: Mon, 22 Oct 2012 02:53:35 -0400 Message-ID: <20121022065335.18883.82505.stgit@ubuntu> In-Reply-To: <20121022065301.18883.35308.stgit@ubuntu> References: <20121022065301.18883.35308.stgit@ubuntu> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmDTnHRMZSnOFigdFN6Q09A+7KqdL+LLY3zstvjgH6fDJML9p0loiurk77Kim/JC3h/z/Up X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marc Zyngier X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Marc Zyngier Do the necessary save/restore dance for the timers in the world switch code. In the process, allow the guest to read the physical counter, which is useful for its own clock_event_device. Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kernel/asm-offsets.c | 8 ++++++++ arch/arm/kvm/arm.c | 3 +++ arch/arm/kvm/interrupts_head.S | 41 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index fba332b..813d386 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -177,6 +177,14 @@ int main(void) DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr)); DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr)); DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); +#ifdef CONFIG_KVM_ARM_TIMER + DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl)); + DEFINE(VCPU_TIMER_CNTV_CVALH, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval32.high)); + DEFINE(VCPU_TIMER_CNTV_CVALL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval32.low)); + DEFINE(KVM_TIMER_CNTVOFF_H, offsetof(struct kvm, arch.timer.cntvoff32.high)); + DEFINE(KVM_TIMER_CNTVOFF_L, offsetof(struct kvm, arch.timer.cntvoff32.low)); + DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled)); +#endif DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base)); #endif DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index cab9cb7..09b7072 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -660,6 +660,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) update_vttbr(vcpu->kvm); kvm_vgic_sync_to_cpu(vcpu); + kvm_timer_sync_to_cpu(vcpu); local_irq_disable(); @@ -673,6 +674,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) { local_irq_enable(); + kvm_timer_sync_from_cpu(vcpu); kvm_vgic_sync_from_cpu(vcpu); continue; } @@ -712,6 +714,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) * Back from guest *************************************************************/ + kvm_timer_sync_from_cpu(vcpu); kvm_vgic_sync_from_cpu(vcpu); ret = handle_exit(vcpu, run, ret); diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index 0003aab..ece84d1 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -422,6 +422,25 @@ #define CNTHCTL_PL1PCEN (1 << 1) .macro save_timer_state vcpup +#ifdef CONFIG_KVM_ARM_TIMER + ldr r4, [\vcpup, #VCPU_KVM] + ldr r2, [r4, #KVM_TIMER_ENABLED] + cmp r2, #0 + beq 1f + + mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL + and r2, #3 + str r2, [\vcpup, #VCPU_TIMER_CNTV_CTL] + bic r2, #1 @ Clear ENABLE + mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL + isb + + mrrc p15, 3, r2, r3, c14 @ CNTV_CVAL + str r3, [\vcpup, #VCPU_TIMER_CNTV_CVALH] + str r2, [\vcpup, #VCPU_TIMER_CNTV_CVALL] + +1: +#endif @ Allow physical timer/counter access for the host mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN) @@ -435,6 +454,28 @@ orr r2, r2, #CNTHCTL_PL1PCTEN bic r2, r2, #CNTHCTL_PL1PCEN mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL + +#ifdef CONFIG_KVM_ARM_TIMER + ldr r4, [\vcpup, #VCPU_KVM] + ldr r2, [r4, #KVM_TIMER_ENABLED] + cmp r2, #0 + beq 1f + + ldr r3, [r4, #KVM_TIMER_CNTVOFF_H] + ldr r2, [r4, #KVM_TIMER_CNTVOFF_L] + mcrr p15, 4, r2, r3, c14 @ CNTVOFF + isb + + ldr r3, [\vcpup, #VCPU_TIMER_CNTV_CVALH] + ldr r2, [\vcpup, #VCPU_TIMER_CNTV_CVALL] + mcrr p15, 3, r2, r3, c14 @ CNTV_CVAL + + ldr r2, [\vcpup, #VCPU_TIMER_CNTV_CTL] + and r2, #3 + mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL + isb +1: +#endif .endm /* Configures the HSTR (Hyp System Trap Register) on entry/return