From patchwork Wed Oct 24 00:33:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Cartwright X-Patchwork-Id: 1635201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 924DB3FD85 for ; Wed, 24 Oct 2012 00:35:45 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQov7-0005ay-4M; Wed, 24 Oct 2012 00:34:05 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TQov4-0005aR-B1 for linux-arm-kernel@merlin.infradead.org; Wed, 24 Oct 2012 00:34:02 +0000 Received: from mailserver5.natinst.com ([130.164.80.5] helo=spamkiller05.natinst.com) by casper.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQouz-0002fo-Nx for linux-arm-kernel@lists.infradead.org; Wed, 24 Oct 2012 00:34:01 +0000 Received: from mailserv59-us.natinst.com (nb-hsrp-1338.natinst.com [130.164.19.133]) by spamkiller05.natinst.com (8.14.5/8.14.5) with ESMTP id q9O0Xmf7024182; Tue, 23 Oct 2012 19:33:48 -0500 Received: from beefymiracle.amer.corp.natinst.com ([130.164.14.197]) by mailserv59-us.natinst.com (Lotus Domino Release 8.5.3FP2 HF169) with ESMTP id 2012102319334929-570846 ; Tue, 23 Oct 2012 19:33:49 -0500 Received: by beefymiracle.amer.corp.natinst.com (Postfix, from userid 1000) id 7CE05600D2; Tue, 23 Oct 2012 19:33:53 -0500 (CDT) Date: Tue, 23 Oct 2012 19:33:53 -0500 From: Josh Cartwright To: arm@kernel.org, Arnd Bergmann Subject: [PATCH v3 1/5] zynq: use GIC device tree bindings Message-ID: <20121024003353.GB31625@beefymiracle.amer.corp.natinst.com> MIME-Version: 1.0 In-Reply-To: <20121024003218.GA31625@beefymiracle.amer.corp.natinst.com> User-Agent: Mutt/1.5.21 (2011-07-01) X-MIMETrack: Itemize by SMTP Server on MailServ59-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 10/23/2012 07:33:49 PM, Serialize by Router on MailServ59-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 10/23/2012 07:33:49 PM, Serialize complete at 10/23/2012 07:33:49 PM Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.7.7855, 1.0.431, 0.0.0000 definitions=2012-10-23_09:2012-10-23, 2012-10-23, 1970-01-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121024_013358_399001_87096C61 X-CRM114-Status: GOOD ( 13.76 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-1.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nick Bowler , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, John Linn X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode register addresses. Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann --- arch/arm/boot/dts/zynq-ep107.dts | 8 +++++--- arch/arm/mach-zynq/common.c | 7 ++++++- arch/arm/mach-zynq/include/mach/zynq_soc.h | 2 -- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts index 37ca192..7bfff4a 100644 --- a/arch/arm/boot/dts/zynq-ep107.dts +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -36,10 +36,12 @@ ranges; intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; interrupt-controller; - compatible = "arm,gic"; - reg = <0xF8F01000 0x1000>; - #interrupt-cells = <2>; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; }; uart0: uart@e0000000 { diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index ab5cfdd..d73963b 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -55,12 +55,17 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } +static struct of_device_id irq_match[] __initdata = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { } +}; + /** * xilinx_irq_init() - Interrupt controller initialization for the GIC. */ static void __init xilinx_irq_init(void) { - gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); + of_irq_init(irq_match); } /* The minimum devices needed to be mapped before the VM system is up and diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index d0d3f8f..3d1c6a6 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -35,8 +35,6 @@ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) -#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) #define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) /*