From patchwork Wed Oct 31 17:25:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johannes Stezenbach X-Patchwork-Id: 1680561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 8A1D53FDDA for ; Wed, 31 Oct 2012 17:28:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TTc3k-0003wL-Qr; Wed, 31 Oct 2012 17:26:33 +0000 Received: from [2a02:8b8:656::164] (helo=bar.sig21.net) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TTc3i-0003vg-4Q for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2012 17:26:30 +0000 Received: from p5099b351.dip0.t-ipconnect.de ([80.153.179.81] helo=zzz.local) by bar.sig21.net with esmtpsa (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.72) (envelope-from ) id 1TTc39-0000mT-D6; Wed, 31 Oct 2012 18:26:04 +0100 Received: from js by zzz.local with local (Exim 4.80) (envelope-from ) id 1TTc38-0005Sn-1d; Wed, 31 Oct 2012 18:25:54 +0100 Date: Wed, 31 Oct 2012 18:25:54 +0100 From: Johannes Stezenbach To: Russell King - ARM Linux Subject: [PATCH v2] fix DEBUG_LL DCC race condition Message-ID: <20121031172553.GA20949@sig21.net> References: <20121029151832.GA2162@sig21.net> <20121031163615.GQ21164@n2100.arm.linux.org.uk> <20121031170853.GA20498@sig21.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20121031170853.GA20498@sig21.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-21-Score: -2.9 (--) X-Spam-21-Report: No, score=-2.9 required=8.0 tests=ALL_TRUSTED=-1, BAYES_00=-1.9 autolearn=ham X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121031_132630_377552_DA0C36B1 X-CRM114-Status: GOOD ( 11.00 ) X-Spam-Score: -1.1 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.8 RDNS_NONE Delivered to internal network by a host with no rDNS Cc: Tony Lindgren , linux-arm-kernel@lists.infradead.org, Rob Herring X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Trying to boot a kernel with I- and D-caches disabled sometimes hangs when DEBUG_LL output to DCC is enabled. Apparently the JTAG debugger sometimes reads the DCC register before the current busyuart implementation could see the wDTRfull flag, thus busyuart spins in an endless loop. The reason seems to be a misunderstanding of the purpose of the busyuart macro. For UART, waituart should wait until flow control allows to send the character, or do nothing. busyuart should wait until the FIFO is empty (all data is sent). For DCC, busyuart should wait until the JTAG debugger has read the DCC register (wait for wDTRfull == 0 on ARMv6), and waituart does nothing. Signed-off-by: Johannes Stezenbach --- v2: - update description - waituart is empty (no flow control) diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S index 43afcb0..30e18e5 100644 --- a/arch/arm/include/debug/icedcc.S +++ b/arch/arm/include/debug/icedcc.S @@ -21,13 +21,6 @@ .endm .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c0, c1, 0 - tst \rx, #0x20000000 - beq 1001b - .endm - - .macro waituart, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 @@ -38,6 +31,9 @@ 1002: .endm + .macro waituart, rd, rx + .endm + #elif defined(CONFIG_CPU_XSCALE) .macro senduart, rd, rx @@ -45,13 +41,6 @@ .endm .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c14, c0, 0 - tst \rx, #0x10000000 - beq 1001b - .endm - - .macro waituart, rd, rx mov \rd, #0x10000000 1001: subs \rd, \rd, #1 @@ -62,6 +51,9 @@ 1002: .endm + .macro waituart, rd, rx + .endm + #else .macro senduart, rd, rx @@ -69,14 +61,6 @@ .endm .macro busyuart, rd, rx -1001: - mrc p14, 0, \rx, c0, c0, 0 - tst \rx, #2 - beq 1001b - - .endm - - .macro waituart, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 @@ -87,4 +71,7 @@ 1002: .endm + .macro waituart, rd, rx + .endm + #endif /* CONFIG_CPU_V6 */