From patchwork Sat Nov 3 16:33:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Nesterov X-Patchwork-Id: 1692801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 558A93FD4E for ; Sat, 3 Nov 2012 16:34:03 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUgdx-0006vW-58; Sat, 03 Nov 2012 16:32:22 +0000 Received: from mx1.redhat.com ([209.132.183.28]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TUgdt-0006tx-Gr for linux-arm-kernel@lists.infradead.org; Sat, 03 Nov 2012 16:32:19 +0000 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qA3GW4Qe015400 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Sat, 3 Nov 2012 12:32:04 -0400 Received: from tranklukator.brq.redhat.com (dhcp-1-232.brq.redhat.com [10.34.1.232]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id qA3GW1do006846; Sat, 3 Nov 2012 12:32:02 -0400 Received: by tranklukator.brq.redhat.com (nbSMTP-1.00) for uid 500 oleg@redhat.com; Sat, 3 Nov 2012 17:33:04 +0100 (CET) Date: Sat, 3 Nov 2012 17:33:01 +0100 From: Oleg Nesterov To: Ananth N Mavinakayanahalli Subject: Re: [PATCH 6/9] uprobes: flush cache after xol write Message-ID: <20121103163301.GA9496@redhat.com> References: <1350242593-17761-1-git-send-email-rabin@rab.in> <1350242593-17761-6-git-send-email-rabin@rab.in> <20121015165756.GA11737@redhat.com> <20121025145839.GB26929@redhat.com> <20121026055239.GA4862@in.ibm.com> <20121026163951.GA17742@redhat.com> <20121029053522.GC3400@in.ibm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20121029053522.GC3400@in.ibm.com> User-Agent: Mutt/1.5.18 (2008-05-17) X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121103_123217_741823_7E758209 X-CRM114-Status: GOOD ( 21.20 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [209.132.183.28 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Rabin Vincent , Peter Zijlstra , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Srikar Dronamraju X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 10/29, Ananth N Mavinakayanahalli wrote: > > On Fri, Oct 26, 2012 at 06:39:51PM +0200, Oleg Nesterov wrote: > > > > > > > OTOH, I do not understand this stuff, everything is nop on x86. And > > > > when I look into Documentation/cachetlb.txt I am starting to think > > > > that may be this needs flush_icache_user_range instead? > > > > > > > > Rabin, Ananth could you clarify this? > > > > > > Yes. We need flush_icache_user_range(). Though for x86 its always been a > > > nop, one never knows if there is some Power4 or older machine out there > > > that is still being used. We are fine for Power5 and later. > > > > This is bad... > > > > flush_icache_user needs vma. perhaps just to check VM_EXEC... > > > > So let me repeat to be sure I really understand, do you confirm that > > _in general_ flush_dcache_page() is not enough? > > flush_dcache_page() on powerpc already checks for > CPU_FTR_COHERENT_ICACHE. So, yes, that is enough. Thanks Ananth. Still it is not clear to me if flush_dcache_page() would be always right if we add the new port. OK. So I assume we need the fix and I am going to apply the patch below. Ananth, Rabin, will you ack it (including the comment I affed) ? Oleg. ------------------------------------------------------------------------------ [PATCH] uprobes: flush cache after xol write From: Rabin Vincent Flush the cache so that the instructions written to the XOL area are visible. Signed-off-by: Rabin Vincent Acked-by: Ananth N Mavinakayanahalli --- x/kernel/events/uprobes.c +++ x/kernel/events/uprobes.c @@ -1199,6 +1199,11 @@ static unsigned long xol_get_insn_slot(s vaddr = kmap_atomic(area->page); memcpy(vaddr + offset, uprobe->arch.insn, MAX_UINSN_BYTES); kunmap_atomic(vaddr); + /* + * We probably need flush_icache_user_range() but it needs vma. + * This should work on supported architectures too. + */ + flush_dcache_page(area->page); return current->utask->xol_vaddr; }