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[V6,3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

Message ID 201211081408.41983.arnd@arndb.de (mailing list archive)
State New, archived
Headers show

Commit Message

Arnd Bergmann Nov. 8, 2012, 2:08 p.m. UTC 
The newly introduced l2_wt_override should be in the same #ifdef
as the code using it, otherwise we get:

arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
On Tuesday 23 October 2012, Gregory CLEMENT wrote:
> @@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
>  static u32 l2x0_way_mask;      /* Bitmask of active ways */
>  static u32 l2x0_size;
>  static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
> +static int l2_wt_override;
> +
> +/* Aurora don't have the cache ID register available, so we have to
> + * pass it though the device tree */
> +static u32  cache_id_part_number_from_dt;

Comments

Russell King - ARM Linux Nov. 8, 2012, 2:21 p.m. UTC | #1 
On Thu, Nov 08, 2012 at 02:08:41PM +0000, Arnd Bergmann wrote:
> The newly introduced l2_wt_override should be in the same #ifdef
> as the code using it, otherwise we get:
> 
> arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used

This should already be fixed.  I think your patch pre-dates 7547/4.
Arnd Bergmann Nov. 8, 2012, 2:42 p.m. UTC | #2 
On Thursday 08 November 2012, Russell King - ARM Linux wrote:
> On Thu, Nov 08, 2012 at 02:08:41PM +0000, Arnd Bergmann wrote:
> > The newly introduced l2_wt_override should be in the same #ifdef
> > as the code using it, otherwise we get:
> > 
> > arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used
> 
> This should already be fixed.  I think your patch pre-dates 7547/4.

Yes, that's right. I was looking at yesterday's linux-next. It's fixed today.

Thanks,

	Arnd
diff mbox

Patch

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 92ee4a0..6911b8b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -34,7 +34,6 @@  static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
-static int l2_wt_override;
 
 /* Aurora don't have the cache ID register available, so we have to
  * pass it though the device tree */
@@ -424,6 +423,8 @@  void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 }
 
 #ifdef CONFIG_OF
+static int l2_wt_override;
+
 /*
  * Note that the end addresses passed to Linux primitives are
  * noninclusive, while the hardware cache range operations use