From patchwork Thu Nov 8 14:08:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 1716091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id B75DDDF280 for ; Thu, 8 Nov 2012 14:10:43 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWSmv-0000RS-Hr; Thu, 08 Nov 2012 14:08:57 +0000 Received: from moutng.kundenserver.de ([212.227.126.187]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TWSmq-0000Qj-Kt for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 14:08:55 +0000 Received: from klappe2.localnet (deibp9eh1--blueice3n2.emea.ibm.com [195.212.29.180]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0LvRqd-1TMjov3Gyp-0103mG; Thu, 08 Nov 2012 15:08:43 +0100 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V6 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl Date: Thu, 8 Nov 2012 14:08:41 +0000 User-Agent: KMail/1.12.2 (Linux/3.5.0; KDE/4.3.2; x86_64; ; ) References: <20121023090154.GP21164@n2100.arm.linux.org.uk> <508666A6.9040701@free-electrons.com> In-Reply-To: <508666A6.9040701@free-electrons.com> MIME-Version: 1.0 Message-Id: <201211081408.41983.arnd@arndb.de> X-Provags-ID: V02:K0:SSgZ0o1hlcc1RJyieCy79dfRAWRVD+bZth0hSC/DgoZ 7KEtxfD9qlSquWzFLn+Ea3ypYwny4ntxCYQpBi4l1ADjHl9LDl iRkLmvZfZnhvTMhSBbrKuJ+TeKpYi8eARPLGTu0p6BVy/zIHtP tuY/pwITIEmV3e7uNwVMJxK7Sue0uomw8gnAjdAINMNCf8bFlL Y7Vvw/b9PWkWsqc4xRyZI/h+dQcXT/tWPBDKKSXxA6Vv0ZqD+l AvhalppJnCp/5sruW31J3UJMLsY1fe+7pVztgkbdze497g+uVC QPnAAumIm5HBOrwPymUBvTB43kxqqO3oIYWVu1YzTx8Z/7KyTU hvYJVAxBHZVYP42s67Ao= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121108_090853_143998_E2666ED1 X-CRM114-Status: GOOD ( 16.13 ) X-Spam-Score: 1.1 (+) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (1.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.126.187 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Lior Amsalem , Andrew Lunn , Ike Pan , Will Deacon , Nadav Haklai , Ian Molton , David Marlin , Yehuda Yitschak , Jani Monoses , Russell King - ARM Linux , Tawfik Bayouk , Dan Frazier , Barry Song <21cnbao@gmail.com>, Eran Ben-Avi , Li Li , Shadi Ammouri , Leif Lindholm , Sebastian Hesselbarth , Jason Cooper , Jon Masters , Rob Herring , Ben Dooks , Gregory CLEMENT , Thomas Petazzoni , Chris Van Hoof , Nicolas Pitre , Maen Suleiman , Santosh Shilimkar , Olof Johansson X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The newly introduced l2_wt_override should be in the same #ifdef as the code using it, otherwise we get: arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used Signed-off-by: Arnd Bergmann --- On Tuesday 23 October 2012, Gregory CLEMENT wrote: > @@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock); > static u32 l2x0_way_mask; /* Bitmask of active ways */ > static u32 l2x0_size; > static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; > +static int l2_wt_override; > + > +/* Aurora don't have the cache ID register available, so we have to > + * pass it though the device tree */ > +static u32 cache_id_part_number_from_dt; diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 92ee4a0..6911b8b 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -34,7 +34,6 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock); static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; -static int l2_wt_override; /* Aurora don't have the cache ID register available, so we have to * pass it though the device tree */ @@ -424,6 +423,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) } #ifdef CONFIG_OF +static int l2_wt_override; + /* * Note that the end addresses passed to Linux primitives are * noninclusive, while the hardware cache range operations use