From patchwork Tue Dec 11 16:38:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 1862831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 9C98BDFAC4 for ; Tue, 11 Dec 2012 16:42:26 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TiSrD-0001yc-4E; Tue, 11 Dec 2012 16:38:59 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TiSrA-0001xX-Fy for linux-arm-kernel@lists.infradead.org; Tue, 11 Dec 2012 16:38:57 +0000 Received: from mudshark.cambridge.arm.com (mudshark.cambridge.arm.com [10.1.79.58]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id qBBGciki000750; Tue, 11 Dec 2012 16:38:44 GMT Date: Tue, 11 Dec 2012 16:38:43 +0000 From: Will Deacon To: Guennadi Liakhovetski Subject: Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Message-ID: <20121211163843.GH16759@mudshark.cambridge.arm.com> References: <1347986135-17979-1-git-send-email-lorenzo.pieralisi@arm.com> <1347986135-17979-4-git-send-email-lorenzo.pieralisi@arm.com> <20120919134658.GA2111@linaro.org> <20120920102514.GD4588@e102568-lin.cambridge.arm.com> <20120920110439.GB2117@linaro.org> <20121211163313.GG16759@mudshark.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20121211163313.GG16759@mudshark.cambridge.arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121211_113856_793197_1A14255F X-CRM114-Status: GOOD ( 16.69 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.96.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nicolas Pitre , Dave Martin , Lorenzo Pieralisi , Russell King , "linux-sh@vger.kernel.org" , Catalin Marinas , Daniel Lezcano , Amit Kucheria , Simon Horman , Santosh Shilimkar , Colin Cross , "linux-omap@vger.kernel.org" , Wenzeng Chen , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Tue, Dec 11, 2012 at 04:33:13PM +0000, Will Deacon wrote: > On Tue, Dec 11, 2012 at 04:07:56PM +0000, Guennadi Liakhovetski wrote: > > Git bisect identified this patch, in the mainline as > > > > commit dbee0c6fb4c1269b2dfc8b0b7a29907ea7fed560 > > Author: Lorenzo Pieralisi > > Date: Fri Sep 7 11:06:57 2012 +0530 > > > > ARM: kernel: update cpu_suspend code to use cache LoUIS operations > > > > as the culprit of the broken wake up from STR on mackerel, based on an > > sh7372 A8 SoC. .config attached. > > My guess is that because Cortex-A8 does not implement the MP extensions, > the LoUIS field of the CLIDR reads as zero, and the cache isn't flushed at > all (I can see an early exit in v7_flush_dcache_louis). > > Lorenzo -- how is this supposed to work for uniprocessor CPUs? Bah, forgot to ask you if the following patch helps... Will --->8 Tested-by: Guennadi Liakhovetski diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index cd95664..f58248f 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr mov r3, r3, lsr #20 @ r3 = LoUIS * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0