From patchwork Thu Jan 10 12:01:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1959681 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id AFA283FC85 for ; Thu, 10 Jan 2013 12:05:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TtGpV-00024J-Pv; Thu, 10 Jan 2013 12:01:53 +0000 Received: from mail-la0-f52.google.com ([209.85.215.52]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TtGpR-00023K-P0 for linux-arm-kernel@lists.infradead.org; Thu, 10 Jan 2013 12:01:50 +0000 Received: by mail-la0-f52.google.com with SMTP id fq12so458356lab.25 for ; Thu, 10 Jan 2013 04:01:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent:x-gm-message-state; bh=d1oYA/sTSINVXK85qaYIHABkylo7DEylZkL8qKn0tzg=; b=WzdGTKI4USKmu8JMYVocGCf49exjkf9fcduIkOhAtPLcBvenMdCX06vk6TaZjaqI5t tfVCfVBTytYyOVDtbt1+P/Gc0P0HQ1MquYmejpemvwyZPTyjHBlv4wQ1eqln8nRM2MEc h096r2Iy47Pq+U5ViDA+9VsG1D+n/ZwazMqEvwALynupDv5EDJGv8uWbvi/L9EGte3vp EdonJeVx8HLgPTe/75WhnCZDPDCABRGiH6pyLUM1alf3haHpRIFO6rvOt83uhHGzZT2i 7lTsBKcpEane9FSwz9nZT8RHcCu6bBdahkUaeC+llChhxu7zDEGOJuum+k+X1+rir8Vh 5Seg== X-Received: by 10.152.124.15 with SMTP id me15mr69170792lab.5.1357819307097; Thu, 10 Jan 2013 04:01:47 -0800 (PST) Received: from linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id n7sm693511lbz.5.2013.01.10.04.01.44 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 10 Jan 2013 04:01:45 -0800 (PST) Date: Thu, 10 Jan 2013 12:01:44 +0000 From: Dave Martin To: Nicolas Pitre Subject: Re: [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup Message-ID: <20130110120144.GB29952@linaro.org> References: <1357777251-13541-1-git-send-email-nicolas.pitre@linaro.org> <1357777251-13541-4-git-send-email-nicolas.pitre@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1357777251-13541-4-git-send-email-nicolas.pitre@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-Gm-Message-State: ALoCoQkB2ub4LYy7gQwmPSCUfBqhcCpj5c6ncIJNob2ZTNgjfS1UNszOqilUHNh9EmSVFECNBPBY X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130110_070149_998175_A45989F0 X-CRM114-Status: GOOD ( 23.68 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.52 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Wed, Jan 09, 2013 at 07:20:38PM -0500, Nicolas Pitre wrote: > From: Dave Martin > > This provides helper methods to coordinate between CPUs coming down > and CPUs going up, as well as documentation on the used algorithms, > so that cluster teardown and setup > operations are not done for a cluster simultaneously. > > For use in the power_down() implementation: > * __bL_cpu_going_down(unsigned int cluster, unsigned int cpu) > * __bL_outbound_enter_critical(unsigned int cluster) > * __bL_outbound_leave_critical(unsigned int cluster) > * __bL_cpu_down(unsigned int cluster, unsigned int cpu) > > The power_up_setup() helper should do platform-specific setup in > preparation for turning the CPU on, such as invalidating local caches > or entering coherency. It must be assembler for now, since it must > run before the MMU can be switched on. It is passed the affinity level > which should be initialized. > > Because the bL_cluster_sync_struct content is looked-up and modified > with the cache enabled or disabled depending on the code path, it is > crucial to always ensure proper cache maintenance to update main memory > right away. Therefore, any cached write must be followed by a cache clean > operation and any cached read must be preceded by a cache invalidate > operation on the accessed memory. > > To avoid races where a reader would invalidate the cache and discard the > latest update from a writer before that writer had a chance to clean it > to RAM, we simply use cache flush (clean+invalidate) operations > everywhere. > > Also, in order to prevent a cached writer from interfering with an > adjacent non-cached writer, we ensure each state variable is located to > a separate cache line. > > Thanks to Nicolas Pitre and Achin Gupta for the help with this > patch. > > Signed-off-by: Dave Martin > --- > .../arm/big.LITTLE/cluster-pm-race-avoidance.txt | 498 +++++++++++++++++++++ > arch/arm/common/bL_entry.c | 160 +++++++ > arch/arm/common/bL_head.S | 88 +++- > arch/arm/include/asm/bL_entry.h | 62 +++ > 4 files changed, 806 insertions(+), 2 deletions(-) > create mode 100644 Documentation/arm/big.LITTLE/cluster-pm-race-avoidance.txt [...] > diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c [...] > +int __init bL_cluster_sync_init(void (*power_up_setup)(void)) The addition of the affinity level parameter for power_up_setup means that this prototype is not correct. This is not a functional change, since that function is only called from assembler anyway, but it will help avoid confusion. This could fixed by folding the following changes into the patch. Cheers ---Dave diff --git a/arch/arm/common/bL_entry.c b/arch/arm/common/bL_entry.c index 1ea4ec9..05cfdd3 100644 --- a/arch/arm/common/bL_entry.c +++ b/arch/arm/common/bL_entry.c @@ -245,7 +245,8 @@ int __bL_cluster_state(unsigned int cluster) extern unsigned long bL_power_up_setup_phys; -int __init bL_cluster_sync_init(void (*power_up_setup)(void)) +int __init bL_cluster_sync_init( + void (*power_up_setup)(unsigned int affinity_level)) { unsigned int i, j, mpidr, this_cluster; diff --git a/arch/arm/include/asm/bL_entry.h b/arch/arm/include/asm/bL_entry.h index 167394d..c9c29b2 100644 --- a/arch/arm/include/asm/bL_entry.h +++ b/arch/arm/include/asm/bL_entry.h @@ -183,7 +183,8 @@ void __bL_outbound_leave_critical(unsigned int cluster, int state); bool __bL_outbound_enter_critical(unsigned int this_cpu, unsigned int cluster); int __bL_cluster_state(unsigned int cluster); -int __init bL_cluster_sync_init(void (*power_up_setup)(void)); +int __init bL_cluster_sync_init( + void (*power_up_setup)(unsigned int affinity_level)); #endif /* ! __ASSEMBLY__ */ #endif