@@ -30,6 +30,12 @@
};
};
+ timer@e0030600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xe0030600 0x20>;
+ interrupts = <1 1 0xf04>;
+ };
+
gic: interrupt-controller@e0020000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
@@ -31,6 +31,7 @@
#define USIBU2_RSTCTRL 0x0b0
#define USIBU3_RSTCTRL 0x0b4
#define STI_RSTCTRL 0x124
+#define INTAGCLKCTRL 0x40c
#define USIAU0GCLKCTRL 0x4a0
#define USIBU1GCLKCTRL 0x4b8
#define USIBU2GCLKCTRL 0x4bc
@@ -105,7 +106,7 @@ static struct clk sclkdiv_clks[SCLKDIV_N
};
enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
- GCLK_STI_SCLK,
+ GCLK_STI_SCLK, GCLK_INTA_CLK,
GCLK_NR };
#define GCLK_SCLK(_parent, _reg) \
@@ -125,6 +126,7 @@ static struct clk gclk_clks[GCLK_NR] = {
[GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
USIBU3GCLKCTRL),
[GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
+ [GCLK_INTA_CLK] = GCLK_SCLK(&c32k_clk, INTAGCLKCTRL),
};
static int emev2_gclk_enable(struct clk *clk)
@@ -200,6 +202,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
+ CLKDEV_DEV_ID("smp_twd", &gclk_clks[GCLK_INTA_CLK]),
};
void __init emev2_clock_init(void)
@@ -402,10 +402,14 @@ void __init emev2_add_standard_devices(v
ARRAY_SIZE(emev2_late_devices));
}
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak emev2_register_twd(void) { }
+
void __init emev2_timer_init(void)
{
emev2_clock_init();
shmobile_timer_init();
+ emev2_register_twd();
}
static void __init emev2_init_delay(void)
@@ -28,9 +28,18 @@
#include <mach/emev2.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
#define EMEV2_SCU_BASE 0x1e000000
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xe0030600, 17);
+void __init emev2_register_twd(void)
+{
+ twd_local_timer_register(&twd_local_timer);
+}
+#endif
+
static void __cpuinit emev2_secondary_init(unsigned int cpu)
{
gic_secondary_init(0);