From patchwork Tue Mar 12 04:56:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2252981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 26DE4DF23A for ; Tue, 12 Mar 2013 04:53:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UFHAz-0007y0-J8; Tue, 12 Mar 2013 04:51:01 +0000 Received: from mail-da0-x231.google.com ([2607:f8b0:400e:c00::231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UFHAh-0007tg-7x for linux-arm-kernel@lists.infradead.org; Tue, 12 Mar 2013 04:50:45 +0000 Received: by mail-da0-f49.google.com with SMTP id t11so617109daj.8 for ; Mon, 11 Mar 2013 21:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:date:message-id:in-reply-to:references :subject; bh=oD+2a4OpbYmhSjVIkl3eCFHePji6fAzxdjc7qwJ8xA4=; b=tmmS8JQr9R+BkRFxCR35UPReb1banhMQKtlGWnStxqVclcPDCcpjtby2nLF0GWv6yL aRCPw2VfWIOoZNFuqPxA/aKUzcQ6jIYWiMBAB6gQScuiQMFNMc/91nPynSMEVuIEG7NQ kjZZI4zgLd5AqL0mwvVT01cXp1WfQ8zTy2BovtqYIWUoNAbbbTIr43atRd3Tk+4LsZiM dnzEimQZBqM1B7Q5+iY7rnYEtCdU+tBEIYPgwfaO0qi+EGBwACYAneyUNr1UwZVAylYh /7zEUP1wynpL1GpshfeUNsyjPqh7mDAFxn2RhLNuQN32c8MSAJLCSjooMqSEWPqYYGSQ kr6w== X-Received: by 10.68.134.133 with SMTP id pk5mr26583387pbb.209.1363063837821; Mon, 11 Mar 2013 21:50:37 -0700 (PDT) Received: from [127.0.0.1] (FL1-122-135-132-124.tky.mesh.ad.jp. [122.135.132.124]) by mx.google.com with ESMTPS id b9sm23294668pba.6.2013.03.11.21.50.35 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Mar 2013 21:50:36 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Tue, 12 Mar 2013 13:56:28 +0900 Message-Id: <20130312045628.19701.58216.sendpatchset@w520> In-Reply-To: <20130312045559.19701.77841.sendpatchset@w520> References: <20130312045559.19701.77841.sendpatchset@w520> Subject: [PATCH 03/04] ARM: shmobile: r8a73a4 IRQC support X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130312_005043_891639_D1BC80B5 X-CRM114-Status: GOOD ( 11.95 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (magnus.damm[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: kuninori.morimoto.gx@renesas.com, arnd@arndb.de, Magnus Damm , horms@verge.net.au, olof@lixom.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Magnus Damm Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm --- Depends on: [PATCH] irqchip: Renesas IRQC driver [PATCH] irqchip: irqc: Add DT support arch/arm/boot/dts/r8a73a4.dtsi | 32 ++++++++++ arch/arm/mach-shmobile/Kconfig | 1 arch/arm/mach-shmobile/setup-r8a73a4.c | 97 ++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) --- 0002/arch/arm/boot/dts/r8a73a4.dtsi +++ work/arch/arm/boot/dts/r8a73a4.dtsi 2013-03-12 00:42:47.000000000 +0900 @@ -51,4 +51,36 @@ <1 11 0xf08>, <1 10 0xf08>; }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, + <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, + <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, + <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, + <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, + <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, + <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; + }; + + irqc1: interrupt-controller@e61c0200 { + compatible = "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe61c0200 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, + <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, + <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, + <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, + <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, + <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, + <0 56 4>, <0 57 4>; + }; + }; --- 0003/arch/arm/mach-shmobile/Kconfig +++ work/arch/arm/mach-shmobile/Kconfig 2013-03-12 00:42:47.000000000 +0900 @@ -24,6 +24,7 @@ config ARCH_R8A73A4 select CPU_V7 select ARM_ARCH_TIMER select SH_CLK_CPG + select RENESAS_IRQC config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" --- 0002/arch/arm/mach-shmobile/setup-r8a73a4.c +++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-12 00:43:25.000000000 +0900 @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -135,6 +136,100 @@ static struct platform_device scif5_devi }, }; +static struct renesas_irqc_config irqc0_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ +}; + +static struct resource irqc0_resources[] = { + DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ + DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ + DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ + DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ + DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ + DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ + DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ + DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ + DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ + DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ + DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ + DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ + DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ + DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ + DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ + DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ + DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ + DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ + DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ + DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ + DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ + DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ + DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ + DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ + DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ + DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ + DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ + DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ + DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ + DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ +}; + +static struct platform_device irqc0_device = { + .name = "renesas_irqc", + .id = 0, + .resource = irqc0_resources, + .num_resources = ARRAY_SIZE(irqc0_resources), + .dev = { + .platform_data = &irqc0_platform_data, + }, +}; + +static struct renesas_irqc_config irqc1_platform_data = { + .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ +}; + +static struct resource irqc1_resources[] = { + DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ + DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ + DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ + DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ + DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ + DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ + DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ + DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ + DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ + DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ + DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ + DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ + DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ + DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ + DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ + DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ + DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ + DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ + DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ + DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ + DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ + DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ + DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ + DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ + DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ + DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ + DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ +}; + +static struct platform_device irqc1_device = { + .name = "renesas_irqc", + .id = 1, + .resource = irqc1_resources, + .num_resources = ARRAY_SIZE(irqc1_resources), + .dev = { + .platform_data = &irqc1_platform_data, + }, +}; + static struct platform_device *r8a73a4_devices[] __initdata = { &scif0_device, &scif1_device, @@ -142,6 +237,8 @@ static struct platform_device *r8a73a4_d &scif3_device, &scif4_device, &scif5_device, + &irqc0_device, + &irqc1_device, }; void __init r8a73a4_add_standard_devices(void)