From patchwork Mon Mar 18 14:32:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2293571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id E1D58DF215 for ; Mon, 18 Mar 2013 15:23:59 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHbrm-0006Bx-Gp; Mon, 18 Mar 2013 15:20:50 +0000 Received: from mail-da0-x235.google.com ([2607:f8b0:400e:c00::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UHb1D-0000Bn-2a for linux-arm-kernel@lists.infradead.org; Mon, 18 Mar 2013 14:26:33 +0000 Received: by mail-da0-f53.google.com with SMTP id n34so1362854dal.26 for ; Mon, 18 Mar 2013 07:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:date:message-id:in-reply-to:references :subject; bh=69lTODtfLP1+FQueF33fVeNIZqyUGSMlGM/MMgSxCoQ=; b=RMjVQktVWPPHaoH7E5+X2K0cPe/gPsz23UV9In8yFj6iTUyJUTzmuaP2ud34u2dxUJ 8hAntv+vojnt0blS8r+dllGFX+6q5/xcX6c1obTZq0VysUl/A32W05zB39dFL+2Aw4dZ aB8YHXfVj3c4IUtlzM50V/+U+FP9T2kdcE2xZeE20yCzGgoxmthT7Sd/yntG61UUUzKK mX8Ow3+S0JzGnhAsrDxmCdQnEStB5pJmHG1ad5YGvOqG1fWfFXBoqATX/FXLlvl0ncF+ e81ui7Rg2VmQC8izhnFpBmLzSWNfiEH4VwY9hh1TL9Z2RuM3OweP1F0OZ0EMvaFvE/ag bnBA== X-Received: by 10.68.180.193 with SMTP id dq1mr34399974pbc.67.1363616788978; Mon, 18 Mar 2013 07:26:28 -0700 (PDT) Received: from [127.0.0.1] (FLH1All083.tky.mesh.ad.jp. [211.13.49.83]) by mx.google.com with ESMTPS id i10sm20381395pbd.1.2013.03.18.07.26.26 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 18 Mar 2013 07:26:27 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Mon, 18 Mar 2013 23:32:22 +0900 Message-Id: <20130318143222.26687.79780.sendpatchset@w520> In-Reply-To: <20130318143203.26687.98180.sendpatchset@w520> References: <20130318143203.26687.98180.sendpatchset@w520> Subject: [PATCH 02/04] ARM: shmobile: r8a73a4 SCIF support V2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130318_102632_714413_213C8BC3 X-CRM114-Status: GOOD ( 12.43 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (magnus.damm[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: kuninori.morimoto.gx@renesas.com, arnd@arndb.de, Magnus Damm , horms@verge.net.au, olof@lixom.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Magnus Damm Add SCIF serial port support to the r8a73a4 SoC by adding platform devices for SCIFA0 -> SCIFA1 as well as SCIFB0 -> SCIFB3 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm --- Changes since V1: - Replaced static platform devices with array of platform data together with a call to platform_device_register_data() This version is about 70 lines smaller than V1. arch/arm/mach-shmobile/clock-r8a73a4.c | 15 ++++++++++- arch/arm/mach-shmobile/setup-r8a73a4.c | 43 ++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) --- 0003/arch/arm/mach-shmobile/clock-r8a73a4.c +++ work/arch/arm/mach-shmobile/clock-r8a73a4.c 2013-03-18 21:42:19.000000000 +0900 @@ -28,6 +28,7 @@ #define CPG_LEN 0x270 #define MPCKCR 0xe6150080 +#define SMSTPCR2 0xe6150138 static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -53,11 +54,23 @@ static struct clk *main_clks[] = { &extal2_clk, }; -enum { MSTP_NR }; +enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ }; static struct clk_lookup lookups[] = { + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), }; void __init r8a73a4_clock_init(void) --- 0003/arch/arm/mach-shmobile/setup-r8a73a4.c +++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-03-18 21:43:19.000000000 +0900 @@ -21,13 +21,56 @@ #include #include #include +#include #include #include #include #include +#define SCIF_COMMON(scif_type, baseaddr, irq) \ + .type = PORT_SCIFA, \ + .mapbase = baseaddr, \ + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ + .scbrr_algo_id = SCBRR_ALGO_4, \ + .irqs = SCIx_IRQ_MUXED(irq) + +#define SCIFA_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ +} + +#define SCIFB_DATA(index, baseaddr, irq) \ +[index] = { \ + SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ + .scscr = SCSCR_RE | SCSCR_TE, \ +} + +enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; + +static const struct plat_sci_port scif[] = { + SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ + SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ + SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */ + SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ + SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ + SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ +}; + +static inline void r8a73a4_register_scif(int idx) +{ + platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], + sizeof(struct plat_sci_port)); +} + void __init r8a73a4_add_standard_devices(void) { + r8a73a4_register_scif(SCIFA0); + r8a73a4_register_scif(SCIFA1); + r8a73a4_register_scif(SCIFB0); + r8a73a4_register_scif(SCIFB1); + r8a73a4_register_scif(SCIFB2); + r8a73a4_register_scif(SCIFB3); } #ifdef CONFIG_USE_OF