From patchwork Wed Mar 20 13:46:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Machek X-Patchwork-Id: 2307661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 075623FC54 for ; Wed, 20 Mar 2013 13:49:40 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIJLS-00007L-4E; Wed, 20 Mar 2013 13:46:22 +0000 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIJLN-00006z-MC for linux-arm-kernel@lists.infradead.org; Wed, 20 Mar 2013 13:46:19 +0000 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id 2CD50813D3; Wed, 20 Mar 2013 14:46:15 +0100 (CET) Date: Wed, 20 Mar 2013 14:46:12 +0100 From: Pavel Machek To: dinguyen@altera.com Subject: Re: [PATCHv2 2/2] ARM: socfpga: Add clock entries into device tree Message-ID: <20130320134612.GA27793@amd.pavel.ucw.cz> References: <1363707936-17769-1-git-send-email-dinguyen@altera.com> <1363707936-17769-2-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1363707936-17769-2-git-send-email-dinguyen@altera.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130320_094617_845234_C06FF7FB X-CRM114-Status: GOOD ( 11.75 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [195.113.26.193 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: dinh.linux@gmail.com, arnd@arndb.de, olof@lixom.net, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi! > Adds the main PLL clock groups for SOCFPGA into device tree file > so that the clock framework to query the clock and clock rates > appropriately. Is there an easy way to test it? I was keeping modified clk.c with hardcoded clock to have working ethernet; I reverted that patch and applied 2/2, but now NFS root refuses to mount (similar symptoms to missing clk.c modifications). Also I need following patch to get it to compile: commit f85232eec5330e64984facd300ef864c53a326f5 Author: Pavel Machek Date: Wed Mar 20 14:41:59 2013 +0100 Patch needed to get clk.c to compile. Signed-off-by: Pavel Machek Thanks, Pavel diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index da6b461..3504dbf 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -49,6 +49,7 @@ struct socfpga_clk { void __iomem *reg; char *parent_name; char *clk_name; + int fixed_div; }; #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw)