From patchwork Wed Mar 20 15:29:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Machek X-Patchwork-Id: 2308171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 55E3F3FC54 for ; Wed, 20 Mar 2013 15:32:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIKx9-0008Fg-Fu; Wed, 20 Mar 2013 15:29:23 +0000 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UIKx6-0008F5-2j for linux-arm-kernel@lists.infradead.org; Wed, 20 Mar 2013 15:29:20 +0000 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id E3AD1813A0; Wed, 20 Mar 2013 16:29:18 +0100 (CET) Date: Wed, 20 Mar 2013 16:29:15 +0100 From: Pavel Machek To: dinguyen@altera.com Subject: Re: [PATCHv2 1/2] ARM: socfpga: Enable soft reset Message-ID: <20130320152915.GA32083@amd.pavel.ucw.cz> References: <1363707936-17769-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1363707936-17769-1-git-send-email-dinguyen@altera.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130320_112920_329965_041292C1 X-CRM114-Status: GOOD ( 16.36 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [195.113.26.193 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: dinh.linux@gmail.com, arnd@arndb.de, olof@lixom.net, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi! > From: Dinh Nguyen > > Enable a cold or warm reset to the HW from userspace. > > Also fix a few sparse errors: > > warning: symbol 'sys_manager_base_addr' was not declared. Should it be static? > warning: symbol 'rst_manager_base_addr' was not declared. Should it be static? > > Signed-off-by: Dinh Nguyen Tested-by: Pavel Machek Would it make sense to apply something like this? Struct looks cleaner than offset defines... Thanks, Pavel Switch reset manager to using struct (not defines), cleanups. Convert SMP code to use the struct instead of open-coded numbers. Also none of the code is time-critical, so it does not make sense to use __raw_writel variants. Signed-off-by: Pavel Machek diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index d2a251f..f4b6048 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -20,19 +20,21 @@ #ifndef __MACH_CORE_H #define __MACH_CORE_H -#define SOCFPGA_RSTMGR_CTRL 0x04 -#define SOCFPGA_RSTMGR_MODPERRST 0x14 -#define SOCFPGA_RSTMGR_BRGMODRST 0x1c - -/* System Manager bits */ -#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ -#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ -/*MPU Module Reset Register */ -#define RSTMGR_MPUMODRST_CPU0 0x1 /*CPU0 Reset*/ -#define RSTMGR_MPUMODRST_CPU1 0x2 /*CPU1 Reset*/ -#define RSTMGR_MPUMODRST_WDS 0x4 /*Watchdog Reset*/ -#define RSTMGR_MPUMODRST_SCUPER 0x8 /*SCU and periphs reset*/ -#define RSTMGR_MPUMODRST_L2 0x10 /*L2 Cache reset*/ +struct socfpga_rstmgr_hw { + u32 unk; + u32 ctrl; /* 0x04 */ + u32 unk2, unk3; +/* MPU Module Reset Register */ +#define RSTMGR_MPUMODRST_CPU0 0x1 /* CPU0 Reset */ +#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ +#define RSTMGR_MPUMODRST_WDS 0x4 /* Watchdog Reset */ +#define RSTMGR_MPUMODRST_SCUPER 0x8 /* SCU and periphs reset */ +#define RSTMGR_MPUMODRST_L2 0x10 /* L2 Cache reset */ + u32 mpumodrst; /* 0x10 */ + u32 modperrst; /* 0x14 */ + u32 unk5; + u32 bgrmodrst; /* 0x1c */ +}; extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; @@ -41,7 +43,7 @@ extern void socfpga_init_clocks(void); extern void socfpga_sysmgr_init(void); extern void __iomem *sys_manager_base_addr; -extern void __iomem *rst_manager_base_addr; +extern struct socfpga_rstmgr_hw __iomem *rst_manager_base_addr; extern struct smp_operations socfpga_smp_ops; extern char secondary_trampoline, secondary_trampoline_end; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index b41a945..81b8f1e 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -28,7 +28,7 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; -void __iomem *rst_manager_base_addr; +struct socfpga_rstmgr_hw __iomem *rst_manager_base_addr; unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { @@ -89,13 +89,13 @@ static void socfpga_cyclone5_restart(char mode, const char *cmd) { u32 temp; - temp = __raw_readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); + temp = readl(&rst_manager_base_addr->ctrl); if (mode == 'h') - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; + temp |= 1; /* RSTMGR_CTRL_SWCOLDRSTREQ, cold reset */ else - temp |= RSTMGR_CTRL_SWWARMRSTREQ; - __raw_writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); + temp |= 2; /* RSTMGR_CTRL_SWWARMRSTREQ, warm reset */ + writel(temp, &rst_manager_base_addr->ctrl); } static void __init socfpga_cyclone5_init(void) diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index c75c33d..822a93e 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -47,7 +47,7 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct if (cpu1start_addr) { memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); - __raw_writel(virt_to_phys(socfpga_secondary_startup), + writel(virt_to_phys(socfpga_secondary_startup), (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); flush_cache_all(); @@ -55,7 +55,7 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct outer_clean_range(0, trampoline_size); /* This will release CPU #1 out of reset.*/ - __raw_writel(0, rst_manager_base_addr + 0x10); + writel(0, &rst_manager_base_addr->mpumodrst); } return 0; @@ -101,7 +101,7 @@ static void socfpga_cpu_die(unsigned int cpu) flush_cache_all(); /* This will put CPU1 into reset.*/ - __raw_writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + 0x10); + writel(RSTMGR_MPUMODRST_CPU1, &rst_manager_base_addr->mpumodrst); cpu_do_idle();