From patchwork Fri May 3 21:50:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 2519601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 2480CDF2E5 for ; Fri, 3 May 2013 21:51:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYNt3-0003wW-3q; Fri, 03 May 2013 21:51:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYNt0-00015r-0y; Fri, 03 May 2013 21:51:26 +0000 Received: from galois.linutronix.de ([2001:470:1f0b:db:abcd:42:0:1]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYNsu-00013J-FA for linux-arm-kernel@lists.infradead.org; Fri, 03 May 2013 21:51:22 +0000 Received: from localhost ([127.0.0.1] helo=localhost6.localdomain6) by Galois.linutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1UYNsP-0006zI-Po; Fri, 03 May 2013 23:50:49 +0200 Message-Id: <20130503214629.536981253@linutronix.de> User-Agent: quilt/0.48-1 Date: Fri, 03 May 2013 21:50:48 -0000 From: Thomas Gleixner To: LKML Subject: [RFC patch 3/8] genirq: generic chip: Handle separate mask registers References: <20130503212258.385818955@linutronix.de> Content-Disposition: inline; filename=genirq-handle-separate-mask-registers.patch X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130503_175120_944520_ADAC7493 X-CRM114-Status: GOOD ( 12.81 ) X-Spam-Score: -4.5 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , linux-doc@vger.kernel.org, Joey Oravec , Lennert Buytenhek , Russell King - ARM Linux , Jason Gunthorpe , Holger Brunck , Ezequiel Garcia , Grant Likely , Sebastian Hesselbarth , Jason Cooper , Arnd Bergmann , devicetree-discuss@lists.ozlabs.org, Rob Herring , Ben Dooks , Gregory Clement , Simon Guinot , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Jean-Francois Moine , Nicolas Pitre , Gerlando Falauto , Rob Landley , Maxime Ripard X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Gerlando Falauto There are cases where all irq_chip_type instances have separate mask registers, making a shared mask register cache unsuitable for the purpose. Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per chip mask pointer to the per chip private mask cache instead. [ tglx: Simplified code, renamed flag and massaged changelog ] Signed-off-by: Gerlando Falauto Cc: Lennert Buytenhek Cc: Simon Guinot Cc: Joey Oravec Cc: Ben Dooks Cc: Nicolas Pitre Cc: Jason Cooper Cc: Andrew Lunn Cc: Holger Brunck Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Thomas Gleixner --- include/linux/irq.h | 2 ++ kernel/irq/generic-chip.c | 17 ++++++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) Index: linux-2.6/include/linux/irq.h =================================================================== --- linux-2.6.orig/include/linux/irq.h +++ linux-2.6/include/linux/irq.h @@ -704,10 +704,12 @@ struct irq_chip_generic { * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for * irq chips which need to call irq_set_wake() on * the parent irq. Usually GPIO implementations + * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private */ enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, + IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, }; /* Generic chip callback functions */ Index: linux-2.6/kernel/irq/generic-chip.c =================================================================== --- linux-2.6.orig/kernel/irq/generic-chip.c +++ linux-2.6/kernel/irq/generic-chip.c @@ -241,18 +241,21 @@ void irq_setup_generic_chip(struct irq_c { struct irq_chip_type *ct = gc->chip_types; unsigned int i; + u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; raw_spin_lock(&gc_lock); list_add_tail(&gc->list, &gc_list); raw_spin_unlock(&gc_lock); - /* Init mask cache ? */ - if (flags & IRQ_GC_INIT_MASK_CACHE) - gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); - - /* Initialize mask cache pointer */ - for (i = 0; i < gc->num_ct; i++) - ct[i].mask_cache = &gc->mask_cache; + for (i = 0; i < gc->num_ct; i++) { + if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { + mskptr = &ct[i].mask_cache_priv; + mskreg = ct[i].regs.mask; + } + ct[i].mask_cache = mskptr; + if (flags & IRQ_GC_INIT_MASK_CACHE) + *mskptr = irq_reg_readl(gc->reg_base + mskreg); + } for (i = gc->irq_base; msk; msk >>= 1, i++) { if (!(msk & 0x01))