From patchwork Thu Jun 27 17:51:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Drake X-Patchwork-Id: 2794611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 19CD0BF4A1 for ; Thu, 27 Jun 2013 17:51:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A9D4B202FF for ; Thu, 27 Jun 2013 17:51:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD70E202F9 for ; Thu, 27 Jun 2013 17:51:30 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsGLB-0006fG-Um; Thu, 27 Jun 2013 17:50:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsGKr-0007IB-Ru; Thu, 27 Jun 2013 17:50:21 +0000 Received: from lists.laptop.org ([18.85.2.166] helo=swan.laptop.org) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsGKo-0007Gv-Ft for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2013 17:50:18 +0000 Received: from dev.laptop.org (crank.laptop.org [18.85.2.147]) by swan.laptop.org (Postfix) with ESMTP id 18236316A21; Thu, 27 Jun 2013 13:49:29 -0400 (EDT) Received: by dev.laptop.org (Postfix, from userid 1230) id 8A9FEFAACF; Thu, 27 Jun 2013 13:51:18 -0400 (EDT) From: Daniel Drake To: eric.y.miao@gmail.com, haojian.zhuang@gmail.com Subject: [PATCH] mmp: irq: Don't clear unused interrupt enable bits Message-Id: <20130627175118.8A9FEFAACF@dev.laptop.org> Date: Thu, 27 Jun 2013 13:51:18 -0400 (EDT) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130627_135018_570073_CA0146FE X-CRM114-Status: GOOD ( 11.08 ) X-Spam-Score: -5.5 (-----) Cc: pgf@laptop.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When enabling/masking interrupts, the existing MMP2 code clears a mask of 0x7f in the interrupt enable register. The lower 5 bits here are not directly used by Linux: 0:3 is interrupt priority 4 determines whether the interrupt gets delivered to the Security Processor In the OLPC case, a special firmware is running on the SP, and we do not want to mask it from receiving the interrupts it has already unmasked. Refine the mask to only deal with the bits that are of specific interest to Linux running on the main CPU. Signed-off-by: Daniel Drake --- arch/arm/mach-mmp/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c index ac92433..21cc0b5 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq.c @@ -190,7 +190,7 @@ static struct mmp_intc_conf mmp_conf = { static struct mmp_intc_conf mmp2_conf = { .conf_enable = 0x20, .conf_disable = 0x0, - .conf_mask = 0x7f, + .conf_mask = 0x60, }; /* MMP (ARMv5) */