From patchwork Fri Jun 28 11:27:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 2798501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4FF74BF4A1 for ; Fri, 28 Jun 2013 11:33:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 235D020179 for ; Fri, 28 Jun 2013 11:33:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD876201B3 for ; Fri, 28 Jun 2013 11:33:42 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsWvS-0001Ar-B6; Fri, 28 Jun 2013 11:33:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsWqK-0002I2-Bf; Fri, 28 Jun 2013 11:27:56 +0000 Received: from mail-pb0-x22b.google.com ([2607:f8b0:400e:c01::22b]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsWq6-0002Fa-Hp for linux-arm-kernel@lists.infradead.org; Fri, 28 Jun 2013 11:27:43 +0000 Received: by mail-pb0-f43.google.com with SMTP id md12so2144274pbc.30 for ; Fri, 28 Jun 2013 04:27:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=PMYvR+Fpy997ylwBLJMWj5noCE+PSOOdiuewILT/8EE=; b=JQvyjO+rmPEWKPCG+01FDcaVseSZkBERxsGAExsYY+ERNZVTNyBFlTCjJEhLlc3tvE gGPJTks+aNSNtXSpi1cw3p7iZUwX+zhsEzUMuLxVXnFPiP1A8xm3YWzuImY4z8EYnlFz KvZXWshBuW9TsuAx+pikRxEhld0MckOk4pXD9BEG4wB0WDBnbpuEnUjSiplxcNw1e3+s hTw/K+JLw42FwJ9P5QrY3CswfPmzwSf9h8sHraSZLZ4QCKzccguAJ3/O5gUeU20IWfcO MjUhFx7u/LIpzR6pIbpgORkuUdDf98teJ3YnrwngZZ9WwqR4BzvV21O3z8Qr6qlbxUsk 8XyA== X-Received: by 10.68.219.194 with SMTP id pq2mr11054030pbc.151.1372418840977; Fri, 28 Jun 2013 04:27:20 -0700 (PDT) Received: from [127.0.0.1] (ac230065.ppp.asahi-net.or.jp. [183.77.230.65]) by mx.google.com with ESMTPSA id dc3sm7754592pbc.9.2013.06.28.04.27.18 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 28 Jun 2013 04:27:19 -0700 (PDT) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Fri, 28 Jun 2013 20:27:23 +0900 Message-Id: <20130628112723.23809.15876.sendpatchset@w520> In-Reply-To: <20130628112655.23809.39115.sendpatchset@w520> References: <20130628112655.23809.39115.sendpatchset@w520> Subject: [PATCH 03/04] ARM: shmobile: Add r8a73a4 CMT10 clock event X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130628_072742_777758_408F9695 X-CRM114-Status: GOOD ( 12.37 ) X-Spam-Score: -2.0 (--) Cc: olof@lixom.net, horms@verge.net.au, Magnus Damm , arnd@arndb.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Add clock event support for CMT1 timer channel 0 to the r8a73a4 SoC code. The CMT is used together with a 32KHz clock in this case. Signed-off-by: Magnus Damm --- arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +++- arch/arm/mach-shmobile/setup-r8a73a4.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) --- 0001/arch/arm/mach-shmobile/clock-r8a73a4.c +++ work/arch/arm/mach-shmobile/clock-r8a73a4.c 2013-06-28 19:52:50.000000000 +0900 @@ -505,7 +505,7 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, - MSTP323, MSTP318, MSTP317, MSTP316, + MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, MSTP411, MSTP410, MSTP409, MSTP522, MSTP515, @@ -529,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ + [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */ [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ @@ -593,6 +594,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), --- 0001/arch/arm/mach-shmobile/setup-r8a73a4.c +++ work/arch/arm/mach-shmobile/setup-r8a73a4.c 2013-06-28 19:50:40.000000000 +0900 @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -169,6 +170,25 @@ static const struct resource thermal0_re thermal0_resources, \ ARRAY_SIZE(thermal0_resources)) +static struct sh_timer_config cmt10_platform_data = { + .name = "CMT10", + .timer_bit = 0, + .clockevent_rating = 80, +}; + +static struct resource cmt10_resources[] = { + DEFINE_RES_MEM(0xe6130010, 0x0c), + DEFINE_RES_MEM(0xe6130000, 0x04), + DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */ +}; + +#define r8a7790_register_cmt(idx) \ + platform_device_register_resndata(&platform_bus, "sh_cmt", \ + idx, cmt##idx##_resources, \ + ARRAY_SIZE(cmt##idx##_resources), \ + &cmt##idx##_platform_data, \ + sizeof(struct sh_timer_config)) + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -180,6 +200,7 @@ void __init r8a73a4_add_standard_devices r8a73a4_register_irqc(0); r8a73a4_register_irqc(1); r8a73a4_register_thermal(); + r8a7790_register_cmt(10); } #ifdef CONFIG_USE_OF