From patchwork Wed Sep 25 21:30:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 2944741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E193BFF05 for ; Wed, 25 Sep 2013 21:59:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7225F20316 for ; Wed, 25 Sep 2013 21:59:56 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EE6820306 for ; Wed, 25 Sep 2013 21:59:55 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOwgY-0007fR-TN; Wed, 25 Sep 2013 21:31:51 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOwfg-0007gr-3S; Wed, 25 Sep 2013 21:30:56 +0000 Received: from mail-pd0-f171.google.com ([209.85.192.171]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VOwfd-0007fC-OW for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2013 21:30:54 +0000 Received: by mail-pd0-f171.google.com with SMTP id g10so227251pdj.2 for ; Wed, 25 Sep 2013 14:30:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=oS5twnImU3Xj57pJHgF6ZeEBAYE7vkGmo6rhWJCNDw0=; b=FZjf7m4NPUJ3RNXFDkpVpuCNaM8y4eio9wCPj0mQiEEnUtSfhys5sw75JZioyPkdne M9UvLBZ30T5aab7GUfFIkiSwevi5H3D1GSJgmNE8nsnrnViOgTyoWt+IHbH5/lJgRll/ z/eVMdJaRquE97guOFsT0vYhkg6iukDE6298x2Rk6BeKm5j7Z11Mr5aJvSa/+vSLutOw BO0Q6BJx9iog6hTsKv1GFHlA4ElIpoX4h5rrjW261vE9Oyge0jJHFRTQo7mFA9ycxSFC afL6qg6P2UtGslHmpWuFhl214Suh8sEes7Z6is4H8Ttte2nVQ+ZNJrm0YeCXqtaT8axd BAnw== X-Gm-Message-State: ALoCoQm3My1HliXoBRvcEIKs0WnfOK2k2JgCjfz1bD4+qRxLZd3ex/Rw6HpHIAok9craowP83N/2 X-Received: by 10.68.26.130 with SMTP id l2mr4990081pbg.134.1380144628940; Wed, 25 Sep 2013 14:30:28 -0700 (PDT) Received: from localhost (c-67-169-183-77.hsd1.ca.comcast.net. [67.169.183.77]) by mx.google.com with ESMTPSA id ar1sm49780035pbc.34.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 25 Sep 2013 14:30:28 -0700 (PDT) Date: Wed, 25 Sep 2013 14:30:41 -0700 From: Christoffer Dall To: Alexander Graf Subject: Re: [PATCH 8/8] KVM: arm-vgic: Support CPU interface reg access Message-ID: <20130925211150.GH32311@cbox> References: <1377285606-15692-1-git-send-email-christoffer.dall@linaro.org> <1377285606-15692-9-git-send-email-christoffer.dall@linaro.org> <05BF567A-DD8A-4226-A51F-0D661F4D7EB2@suse.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <05BF567A-DD8A-4226-A51F-0D661F4D7EB2@suse.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130925_173053_903346_DCEADFE7 X-CRM114-Status: GOOD ( 21.89 ) X-Spam-Score: -1.9 (-) Cc: linaro-kernel@lists.linaro.org, kvm@vger.kernel.org, patches@linaro.org, Marc Zyngier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sun, Aug 25, 2013 at 04:24:20PM +0100, Alexander Graf wrote: > > On 23.08.2013, at 20:20, Christoffer Dall wrote: > > > Implement support for the CPU interface register access driven by MMIO > > address offsets from the CPU interface base address. Useful for user > > space to support save/restore of the VGIC state. > > > > This commit adds support only for the same logic as the current VGIC > > support, and no more. For example, the active priority registers are > > handled as RAZ/WI, just like setting priorities on the emulated > > distributor. > > > > Signed-off-by: Christoffer Dall > > --- > > virt/kvm/arm/vgic.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 62 insertions(+), 4 deletions(-) > > > > diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c > > index d44b5a1..257dbae 100644 > > --- a/virt/kvm/arm/vgic.c > > +++ b/virt/kvm/arm/vgic.c > > @@ -1684,9 +1684,67 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) > > static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, > > struct kvm_exit_mmio *mmio, phys_addr_t offset) > > { > > - return true; > > + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; > > + u32 reg, mask = 0, shift = 0; > > + bool updated = false; > > + > > + switch (offset & ~0x3) { > > + case GIC_CPU_CTRL: > > + mask = GICH_VMCR_CTRL_MASK; > > + shift = GICH_VMCR_CTRL_SHIFT; > > + break; > > + case GIC_CPU_PRIMASK: > > + mask = GICH_VMCR_PRIMASK_MASK; > > + shift = GICH_VMCR_PRIMASK_SHIFT; > > + break; > > + case GIC_CPU_BINPOINT: > > + mask = GICH_VMCR_BINPOINT_MASK; > > + shift = GICH_VMCR_BINPOINT_SHIFT; > > + break; > > + case GIC_CPU_ALIAS_BINPOINT: > > + mask = GICH_VMCR_ALIAS_BINPOINT_MASK; > > + shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT; > > + break; > > + } > > + > > + if (!mmio->is_write) { > > + reg = (vgic_cpu->vgic_vmcr & mask) >> shift; > > + memcpy(mmio->data, ®, sizeof(reg)); > > + } else { > > + memcpy(®, mmio->data, sizeof(reg)); > > + reg = (reg << shift) & mask; > > + if (reg != (vgic_cpu->vgic_vmcr & mask)) > > + updated = true; > > + vgic_cpu->vgic_vmcr &= ~mask; > > + vgic_cpu->vgic_vmcr |= reg; > > + } > > + return updated; > > +} > > + > > +static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, > > + struct kvm_exit_mmio *mmio, phys_addr_t offset) > > +{ > > + return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); > > +} > > + > > +static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, > > + struct kvm_exit_mmio *mmio, > > + phys_addr_t offset) > > +{ > > + u32 reg; > > + > > + if (mmio->is_write) > > + return false; > > + > > + reg = 0x0002043B; > > This wants a comment and probably also a #define :). > Marc, where does the 0x4b0 product id code come from for the distributor IIDR? Would this be satisfying? Thanks, -Christoffer diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 5214424..558be38 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -71,6 +71,9 @@ #define VGIC_ADDR_UNDEF (-1) #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) +#define GIC_PRODUCT_ID 0x4b0 +#define ARM_JEP106_IMPLEMENTER 0x43b + /* Physical address of vgic virtual cpu interface */ static phys_addr_t vgic_vcpu_base; @@ -331,7 +334,7 @@ static bool handle_mmio_misc(struct kvm_vcpu *vcpu, break; case 8: /* IIDR */ - reg = 0x4B00043B; + reg = (GIC_PRODUCT_ID << 20) | ARM_JEP106_IMPLEMENTER; vgic_reg_access(mmio, ®, word_offset, ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); break; @@ -1734,7 +1737,7 @@ static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, if (mmio->is_write) return false; - reg = 0x0002043B; + reg = (GIC_PRODUCT_ID << 20) | (0x2 << 16) | ARM_JEP106_IMPLEMENTER; mmio_data_write(mmio, ~0, reg); return false; }