From patchwork Thu Oct 10 10:22:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3015101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3EB24BF924 for ; Thu, 10 Oct 2013 10:22:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DCFC12030B for ; Thu, 10 Oct 2013 10:22:19 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 210D7202F0 for ; Thu, 10 Oct 2013 10:22:18 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUDNg-0001RK-I0; Thu, 10 Oct 2013 10:22:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUDNe-00008H-13; Thu, 10 Oct 2013 10:22:06 +0000 Received: from ch1ehsobe006.messaging.microsoft.com ([216.32.181.186] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VUDNc-00007Z-76 for linux-arm-kernel@lists.infradead.org; Thu, 10 Oct 2013 10:22:04 +0000 Received: from mail202-ch1-R.bigfish.com (10.43.68.226) by CH1EHSOBE019.bigfish.com (10.43.70.76) with Microsoft SMTP Server id 14.1.225.22; Thu, 10 Oct 2013 10:21:42 +0000 Received: from mail202-ch1 (localhost [127.0.0.1]) by mail202-ch1-R.bigfish.com (Postfix) with ESMTP id 4A382C01C0; Thu, 10 Oct 2013 10:21:42 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -2 X-BigFish: VS-2(zz98dI1432Izz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de097hz2dh87h2a8h839h944hd25hf0ah1220h1288h12a5h12a9h12bdh137ah13b6h1441h1504h1537h153bh162dh1631h1758h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1fe8h1ff5h209eh1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail202-ch1 (localhost.localdomain [127.0.0.1]) by mail202-ch1 (MessageSwitch) id 1381400500106954_2644; Thu, 10 Oct 2013 10:21:40 +0000 (UTC) Received: from CH1EHSMHS011.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.238]) by mail202-ch1.bigfish.com (Postfix) with ESMTP id 15120200AE; Thu, 10 Oct 2013 10:21:40 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS011.bigfish.com (10.43.70.11) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 10 Oct 2013 10:21:40 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 10 Oct 2013 10:21:39 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.150]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r9AALZAS012504; Thu, 10 Oct 2013 03:21:36 -0700 Date: Thu, 10 Oct 2013 18:22:07 +0800 From: Shawn Guo To: Russell King - ARM Linux Subject: Re: [PATCH] pinctrl: phandle entries will be applied sequentially Message-ID: <20131010102205.GD29191@S2101-09.ap.freescale.net> References: <1381297324-19006-1-git-send-email-shawn.guo@linaro.org> <20131010072624.GA29191@S2101-09.ap.freescale.net> <20131010100840.GP25034@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20131010100840.GP25034@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131010_062204_328749_690D967B X-CRM114-Status: GOOD ( 21.25 ) X-Spam-Score: -1.9 (-) Cc: Sherman Yin , "devicetree@vger.kernel.org" , Linus Walleij , "linux-arm-kernel@lists.infradead.org" , Stephen Warren X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Oct 10, 2013 at 11:08:40AM +0100, Russell King - ARM Linux wrote: > On Thu, Oct 10, 2013 at 03:26:26PM +0800, Shawn Guo wrote: > > However, my patch is talking about a different thing. For example, we > > have a device whose pinctrl-0 consists of two phandle entries that point > > to pin configuration nodes foo and bar. > > > > pinctrl-0 = <&foo &bar>; > > > > foo { > > ... > > }; > > > > bar { > > ... > > }; > > > > My patch only wants to make it clear that the configuration specified by > > node foo will be applied to pin controller first, and the configuration > > defined in node bar will be applied after that. When both nodes have > > configuration for a pin, these two configs for the same pin go to two > > different pinctrl_setting structures. And these two pinctrl_settings > > can not be applied accumulatedly but only sequentially. That's what my > > patch talks about. > > I still say this is a potentially dangerous thing, and in my case of > overriding the DAT3 pull-sense, it will cause the pin to glitch if > nothing is connected to it. > > So even if you do get this clarified, I am *not* happy to change my > patch. What about the solution suggested by Stephen, moving MX6QDL_PAD_SD1_DAT3__SD1_DATA3 out from pinctrl_usdhc1_1 and having additional nodes/phandle for DAT3 with different settings? Shawn diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 59154dc..fd52f4e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1157,7 +1157,6 @@ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 @@ -1165,6 +1164,18 @@ >; }; + pinctrl_usdhc1_1_dat3: usdhc1dat3-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_1_dat3cd: usdhc1dat3cd-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x13059 + >; + }; Then pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3> for existing boards, and <&pinctrl_usdhc1_1 &pinctrl_usdhc1_1_dat3cd> for boards that want to use DAT3 for card detection.