From patchwork Wed Nov 20 18:18:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodolfo Giometti X-Patchwork-Id: 3214701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3711FC045B for ; Wed, 20 Nov 2013 18:20:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7CCAA20780 for ; Wed, 20 Nov 2013 18:20:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03C3D20781 for ; Wed, 20 Nov 2013 18:20:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjCNf-0007Uz-8i; Wed, 20 Nov 2013 18:20:03 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjCNc-0001e5-Mr; Wed, 20 Nov 2013 18:20:00 +0000 Received: from ip-196-116.sn1.eutelia.it ([62.94.196.116] helo=goldrake.enneenne.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjCNY-0001dd-RZ for linux-arm-kernel@lists.infradead.org; Wed, 20 Nov 2013 18:19:58 +0000 Received: from ml.enneenne.com ([192.168.32.10] helo=enneenne.com) by goldrake.enneenne.com with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1Vj6OG-0000rS-Pm; Wed, 20 Nov 2013 12:56:25 +0100 Date: Wed, 20 Nov 2013 19:18:42 +0100 From: Rodolfo Giometti To: Jean-Christophe PLAGNIOL-VILLARD Message-ID: <20131120181841.GQ4578@enneenne.com> References: <1383754767-5398-1-git-send-email-giometti@linux.it> <1384364070-32306-1-git-send-email-nicolas.ferre@atmel.com> <20131114162810.GJ28304@ns203013.ovh.net> <20131114185002.GM10964@enneenne.com> <20131115135256.GP28304@ns203013.ovh.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20131115135256.GP28304@ns203013.ovh.net> Organization: GNU/Linux Device Drivers, Embedded Systems and Courses X-PGP-Key: gpg --keyserver keyserver.linux.it --recv-keys D25A5633 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 192.168.32.10 X-SA-Exim-Mail-From: giometti@enneenne.com X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Subject: Re: [RFC PATCH v2] ARM: at91: add support for Cosino board series by HCE Engineering X-SA-Exim-Version: 4.2.1 (built Mon, 22 Mar 2010 06:51:10 +0000) X-SA-Exim-Scanned: Yes (on goldrake.enneenne.com) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131120_131957_261954_5B17B217 X-CRM114-Status: GOOD ( 20.12 ) X-Spam-Score: -1.9 (-) Cc: Nicolas Ferre , linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Nov 15, 2013 at 02:52:56PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > > +#include "at91sam9g35.dtsi" > > > > + > > > > +/ { > > > > + model = "HCE Cosino core module"; > > > > + compatible = "hce,cosino", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; > > > is this really sam9xek compatible? > > > > Well, the board is derived from ATMEL dev board... maybe I can remove > > these lines... :-/ > > compatible means you board is an extension and that the kernel + dtb will run > on both without modification Ok, at91sam9x5ek dropped. > > + > > + mmc1: mmc@f000c000 { > > + pinctrl-0 = < > > + &pinctrl_board_mmc0 > this will failled you can not have the same pux on 2 device Fixed. Attached a new patch version (V3). ### Changelog V2 -> V3 [Jean-Christophe PLAGNIOL-VILLARD ] * Reference to at91sam9x5ek dropped. * Inavlid mmc1 pinctrl-0 setting fixed V1 -> V2 [Jean-Christophe PLAGNIOL-VILLARD ] * prefix "at91-" added * atmel,mux-mask stuff removed * "compatible" stuff is now on the same line for easy-grep(TM) * lcd binding dropped Ciao, Rodolfo Acked-by: Jean-Christophe PLAGNIOL-VILLARD From 16882a9f85faa21bcd7102894b7829eb4d77f97d Mon Sep 17 00:00:00 2001 From: Rodolfo Giometti Date: Wed, 6 Nov 2013 16:31:50 +0100 Subject: [PATCH] arm mach-at91: add support for Cosino board series by HCE Engineering This patch adds the Cosino at91sam9g35 based CPU module and the Cosino Mega 2560 extension board. Web site: http://www.cosino.it Signed-off-by: Rodolfo Giometti [nicolas.ferre@atmel.com: adapted to newer kernel, modified commit message] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-cosino.dtsi | 121 +++++++++++++++++++++++++++++ arch/arm/boot/dts/at91-cosino_mega2560.dts | 84 ++++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 arch/arm/boot/dts/at91-cosino.dtsi create mode 100644 arch/arm/boot/dts/at91-cosino_mega2560.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ab6a9f5..b05f5e6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb +dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb # sama5d3 dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi new file mode 100644 index 0000000..00e2112 --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -0,0 +1,121 @@ +/* + * cosino.dtsi - Device Tree file for Cosino core module + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9x5ek.dtsi by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +#include "at91sam9g35.dtsi" + +/ { + model = "HCE Cosino core module"; + compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts new file mode 100644 index 0000000..c29c53c --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -0,0 +1,84 @@ +/* + * cosino_mega2560.dts - Device Tree file for Cosino board with Mega 2560 + * extension + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9g35ek.dts by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; +#include "at91-cosino.dtsi" + +/ { + model = "HCE Cosino Mega 2560"; + compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + + tsadcc: tsadcc@f804c000 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + + usart1: serial@f8020000 { + status = "okay"; + }; + + usart2: serial@f8024000 { + status = "okay"; + }; + + usb2: gadget@f803c000 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc1: mmc@f000c000 { + pinctrl-0 = < + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + non-removable; + }; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; +}; -- 1.8.1.2