From patchwork Thu Dec 19 12:49:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 3379941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 40266C0D4A for ; Thu, 19 Dec 2013 12:51:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4B80201C0 for ; Thu, 19 Dec 2013 12:51:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68C582017B for ; Thu, 19 Dec 2013 12:51:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vtd3Y-00004s-Bh; Thu, 19 Dec 2013 12:50:24 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vtd3J-0007gP-T3; Thu, 19 Dec 2013 12:50:09 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vtd3G-0007eB-Hv for linux-arm-kernel@lists.infradead.org; Thu, 19 Dec 2013 12:50:07 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 19 Dec 2013 04:49:45 -0800 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 19 Dec 2013 04:51:49 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 19 Dec 2013 04:51:49 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.327.1; Thu, 19 Dec 2013 04:49:44 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 19 Dec 2013 04:49:44 -0800 Received: from [127.0.1.1] (tamien.nvidia.com [172.17.186.57]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rBJCniEK016099; Thu, 19 Dec 2013 04:49:44 -0800 (PST) Subject: [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file From: Paul Walmsley To: , Date: Thu, 19 Dec 2013 04:49:44 -0800 Message-ID: <20131219124929.3226.79335.stgit@tamien> In-Reply-To: <20131219122857.3226.42830.stgit@tamien> References: <20131219122857.3226.42830.stgit@tamien> User-Agent: StGit/0.17.1-1-g74fd MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131219_075006_673064_3AA2CD8C X-CRM114-Status: GOOD ( 10.42 ) X-Spam-Score: -2.4 (--) Cc: Mark Rutland , Pawel Moll , Ian Campbell , Rob Herring , Kumar Gala , Matthew Longnecker X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect the DFLL (and FCPU cluster) voltage regulator. Signed-off-by: Paul Walmsley Cc: Matthew Longnecker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala --- .../bindings/clock/nvidia,tegra114-dfll.txt | 16 ++++++++++++++++ arch/arm/boot/dts/tegra114-dalmore.dts | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt index b868bf97bc3d..c4072b3f16fc 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt @@ -41,3 +41,19 @@ dfll@70110000 { status = "disabled"; }; +... + +NVIDIA Tegra114 DFLL clocksource data in the board DTS file + +Optional properties: + +- status : device availability -- managed by the DT integration code, not + the DFLL driver. Should be set to "okay" if the DFLL is to be + used on this board type. + + +Example: + +dfll@70110000 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 88be40cf8845..2e8e7ae60c1a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1063,6 +1063,10 @@ }; }; + dfll@70110000 { + status = "okay"; + }; + sdhci@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>;