From patchwork Tue Feb 4 22:00:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 3581441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8F4D69F2E9 for ; Tue, 4 Feb 2014 22:01:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B679320170 for ; Tue, 4 Feb 2014 22:01:35 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B06BD20145 for ; Tue, 4 Feb 2014 22:01:34 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAo3N-0007ws-K5; Tue, 04 Feb 2014 22:01:13 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAo3L-0004bI-4o; Tue, 04 Feb 2014 22:01:11 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAo3I-0004aI-AP for linux-arm-kernel@lists.infradead.org; Tue, 04 Feb 2014 22:01:09 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 8288713EFD1; Tue, 4 Feb 2014 22:00:46 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 7664013F031; Tue, 4 Feb 2014 22:00:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (i-global252.qualcomm.com [199.106.103.252]) (using SSLv3 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0CD1013EFD1; Tue, 4 Feb 2014 22:00:46 +0000 (UTC) Date: Tue, 4 Feb 2014 14:00:45 -0800 From: Stephen Boyd To: John Stultz Subject: Re: Weird sched_clock behaviour during boot with -rc1 Message-ID: <20140204220045.GC20528@codeaurora.org> References: <20140204183641.GA25127@mudshark.cambridge.arm.com> <52F1518B.9010109@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <52F1518B.9010109@linaro.org> User-Agent: Mutt/1.5.20 (2009-06-14) X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140204_170108_513819_8B477F67 X-CRM114-Status: GOOD ( 25.88 ) X-Spam-Score: -2.5 (--) Cc: Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On 02/04, John Stultz wrote: > On 02/04/2014 10:36 AM, Will Deacon wrote: > > Hi guys, > > > > Booting -rc1 on my TC2 gives the following strange entries in the dmesg: > > > > > > Uncompressing Linux... done, booting the kernel. > > [ 0.000000] Booting Linux on physical CPU 0x0 > > > > [...] > > > > [ 0.000000] HighMem zone: 329728 pages, LIFO batch:31 > > [ 7.789662] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns > > [ 0.000129] PERCPU: Embedded 9 pages/cpu @ee7bd000 s12800 r8192 d15872 u36864 > > > > [...] > > > > [ 0.868297] NR_IRQS:16 nr_irqs:16 16 > > [ 0.886350] Architected cp15 timer(s) running at 24.00MHz (phys). > > [ 2915.164998] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 2863311519744ns > > [ 0.000002] Switching to timer-based delay loop > > [ 0.014249] Console: colour dummy device 80x30 > > > > > > so it looks like something whacky goes on during sched_clock registration. > > Sure enough, we're doing a pr_info in-between updating cs.* and calling > > update_sched_clock(), so moving the print sorts things out (diff below). > > Yea... we have to be particularly careful with sched_clock to avoid > locks since we don't want to deadlock, but in this case > sched_clock_register is a little too relaxed here. > > Stephen: Would it make sense to set cd.suspended = true at the top of > the registration? That should block any sched_clock calls from getting > half-updated data, but still allow the sched_clock_update function to work. > That would work, but why can't we just hold the write seqlock during the registration? We would need to make a lockeless version of update_sched_clock() but that doesn't look too hard. It might actually turn out nicer because we call update_sched_clock() here just to set the epoch_cyc but we have to reset the epoch_ns back to 0 to start the count off right. How about this? The only concern is calling read_sched_clock() inside the seqlock, but I don't think that's a concern and if it is we can call it outside the lock at the beginning of this function. ----8<---- diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c index 0abb36464281..ae8f10a02c32 100644 --- a/kernel/time/sched_clock.c +++ b/kernel/time/sched_clock.c @@ -124,6 +124,7 @@ void __init sched_clock_register(u64 (*read)(void), int bits, return; WARN_ON(!irqs_disabled()); + raw_write_seqcount_begin(&cd.seq); read_sched_clock = read; sched_clock_mask = CLOCKSOURCE_MASK(bits); cd.rate = rate; @@ -147,15 +148,16 @@ void __init sched_clock_register(u64 (*read)(void), int bits, /* calculate the ns resolution of this counter */ res = cyc_to_ns(1ULL, cd.mult, cd.shift); - pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lluns\n", - bits, r, r_unit, res, wrap); - - update_sched_clock(); /* * Ensure that sched_clock() starts off at 0ns */ cd.epoch_ns = 0; + cd.epoch_cyc = read_sched_clock(); + raw_write_seqcount_end(&cd.seq); + + pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lluns\n", + bits, r, r_unit, res, wrap); /* Enable IRQ time accounting if we have a fast enough sched_clock */