From patchwork Wed Feb 26 23:13:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 3728941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7F0ADBF13A for ; Wed, 26 Feb 2014 23:13:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 741EE2020F for ; Wed, 26 Feb 2014 23:13:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4EDFC200E9 for ; Wed, 26 Feb 2014 23:13:21 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIner-0001v0-7J; Wed, 26 Feb 2014 23:12:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WInei-0003RJ-EC; Wed, 26 Feb 2014 23:12:48 +0000 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIneY-0003P8-LL for linux-arm-kernel@lists.infradead.org; Wed, 26 Feb 2014 23:12:42 +0000 Received: by mail-pd0-f174.google.com with SMTP id y13so1577113pdi.19 for ; Wed, 26 Feb 2014 15:12:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:in-reply-to:references:subject; bh=msKXdy+BxXEHRE761dmGPtykDCq3lJdArV/wBYAeCNU=; b=u5o7/pAI8/YXBKo3Zs/bMhXLWuOCxgC1Ks0f2dFRKpwv/1cBg1RT6UGw/EXDB2s+TO Z2SEOr/VGNQMe+xOdyRbe3SdS0+pQTJ6tQ1sOSoHd04m0+qgw3SZKak0Q7MiJQ1qNHnY v+D5a5EwXRH6l2DIAyCjJHGTJLfMrZk9zB4Ub6eA36d1RiNVkJ6IxkVk7v9q/KIZ9Re9 d8HSRIPUFj3iQoRwyLHi5YpbJAunWHi0hJYrn0Z5G3pPzU4We8INbfs4MUyYO+pesPM5 FoEDMb2D5aq8tRghdsC4dRNWfrgkh0v2qsQoyBZ+rFHtkt0Gc7hOvhDTvVimAHtO13wJ Qv9Q== X-Received: by 10.66.119.172 with SMTP id kv12mr11765061pab.34.1393456337302; Wed, 26 Feb 2014 15:12:17 -0800 (PST) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by mx.google.com with ESMTPSA id zc6sm16426793pab.18.2014.02.26.15.12.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Feb 2014 15:12:16 -0800 (PST) From: Magnus Damm To: linux-sh@vger.kernel.org Date: Thu, 27 Feb 2014 08:13:35 +0900 Message-Id: <20140226231335.4303.85826.sendpatchset@w520> In-Reply-To: <20140226231326.4303.71886.sendpatchset@w520> References: <20140226231326.4303.71886.sendpatchset@w520> Subject: [PATCH 01/02] ARM: shmobile: Hook in MCPM and CCI to APMU code X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140226_181238_951307_6249545D X-CRM114-Status: GOOD ( 18.97 ) X-Spam-Score: -2.0 (--) Cc: horms@verge.net.au, Magnus Damm , linux-arm-kernel@lists.infradead.org, Sudeep.Holla@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm Add MCPM and CCI hooks to the shared APMU code to allow multicluster operation on r8a7790. Tested with SMP boot and CPU Hotplug on r8a7790 Lager. Signed-off-by: Magnus Damm --- arch/arm/mach-shmobile/headsmp.S | 7 + arch/arm/mach-shmobile/include/mach/common.h | 1 arch/arm/mach-shmobile/platsmp-apmu.c | 111 ++++++++++++++++++++++++-- arch/arm/mach-shmobile/platsmp.c | 4 4 files changed, 116 insertions(+), 7 deletions(-) --- 0001/arch/arm/mach-shmobile/headsmp.S +++ work/arch/arm/mach-shmobile/headsmp.S 2014-02-27 00:57:50.000000000 +0900 @@ -19,6 +19,13 @@ ENTRY(shmobile_invalidate_start) b secondary_startup ENDPROC(shmobile_invalidate_start) +#ifdef CONFIG_MCPM +ENTRY(shmobile_invalidate_mcpm_entry) + bl v7_invalidate_l1 + b mcpm_entry_point +ENDPROC(shmobile_invalidate_mcpm_entry) +#endif + /* * Reset vector for secondary CPUs. * This will be mapped at address 0 by SBAR register. --- 0001/arch/arm/mach-shmobile/include/mach/common.h +++ work/arch/arm/mach-shmobile/include/mach/common.h 2014-02-27 00:57:50.000000000 +0900 @@ -16,6 +16,7 @@ extern void shmobile_smp_hook(unsigned i unsigned long arg); extern int shmobile_smp_cpu_disable(unsigned int cpu); extern void shmobile_invalidate_start(void); +extern void shmobile_invalidate_mcpm_entry(void); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); extern void shmobile_smp_scu_cpu_die(unsigned int cpu); --- 0001/arch/arm/mach-shmobile/platsmp-apmu.c +++ work/arch/arm/mach-shmobile/platsmp-apmu.c 2014-02-27 00:57:50.000000000 +0900 @@ -7,22 +7,28 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include #include #include +#include #include #include #include #include +#include #include #include -static struct { +static struct apmu_cpu { void __iomem *iomem; int bit; } apmu_cpus[CONFIG_NR_CPUS]; +#define MAX_NR_CLUSTERS 2 +static struct apmu_cpu *apmu_clst2cpu[MAX_NR_CLUSTERS][CONFIG_NR_CPUS]; + #define WUPCR_OFFS 0x10 #define PSTR_OFFS 0x40 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) @@ -69,14 +75,23 @@ static int apmu_wrap(int cpu, int (*fn)( static void apmu_init_cpu(struct resource *res, int cpu, int bit) { + u32 id; + int mcpm_cpu, mcpm_cluster; + if (apmu_cpus[cpu].iomem) return; apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res)); apmu_cpus[cpu].bit = bit; - pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit, - res->start, resource_size(res)); + id = cpu_logical_map(cpu); + mcpm_cpu = MPIDR_AFFINITY_LEVEL(id, 0); + mcpm_cluster = MPIDR_AFFINITY_LEVEL(id, 1); + + pr_debug("apmu ioremap %d %d %pr %d %d\n", + cpu, bit, res, mcpm_cluster, mcpm_cpu); + + apmu_clst2cpu[mcpm_cluster][mcpm_cpu] = &apmu_cpus[cpu]; } static struct { @@ -93,7 +108,8 @@ static struct { } }; -static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit)) +static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), + bool allow_multicluster) { u32 id; int k; @@ -110,7 +126,8 @@ static void apmu_parse_cfg(void (*fn)(st is_allowed = true; } } - if (!is_allowed) + + if (!allow_multicluster && !is_allowed) continue; for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { @@ -124,14 +141,19 @@ static void apmu_parse_cfg(void (*fn)(st } } +static int __init shmobile_smp_apmu_cci_init(void); + void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus) { /* install boot code shared by all CPUs */ shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); shmobile_boot_arg = MPIDR_HWID_BITMASK; - /* perform per-cpu setup */ - apmu_parse_cfg(apmu_init_cpu); + /* allow multi-cluster operation in case CCI is detected */ + if (IS_ENABLED(CONFIG_ARM_CCI) && !shmobile_smp_apmu_cci_init()) + apmu_parse_cfg(apmu_init_cpu, true); + else + apmu_parse_cfg(apmu_init_cpu, false); } int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -192,4 +214,79 @@ int shmobile_smp_apmu_cpu_kill(unsigned { return apmu_wrap(cpu, apmu_power_off_poll); } +#else +#define shmobile_smp_apmu_cpu_die() shmobile_smp_sleep() +static inline int shmobile_smp_apmu_cpu_kill(void) { return -ENOTSUPP; } #endif + +#if defined(CONFIG_MCPM) && defined(CONFIG_ARM_CCI) +static void __naked apmu_power_up_setup(unsigned int affinity_level) +{ + asm volatile ("cmp r0, #1\n" + "bxne lr\n" + "b cci_enable_port_for_self "); +} + +static int apmu_power_up(unsigned int cpu, unsigned int cluster) +{ + struct apmu_cpu *ac = apmu_clst2cpu[cluster][cpu]; + if (!ac) + return -EINVAL; + + shmobile_smp_hook(ac - &apmu_cpus[0], + virt_to_phys(shmobile_invalidate_mcpm_entry), 0); + + return apmu_wrap(ac - &apmu_cpus[0], apmu_power_on); +} + +static void apmu_power_down(void) +{ + shmobile_smp_apmu_cpu_die(smp_processor_id()); +} + +static int apmu_power_down_finish(unsigned int cpu, unsigned int cluster) +{ + struct apmu_cpu *ac = apmu_clst2cpu[cluster][cpu]; + int ret = -EINVAL; + + if (ac) + ret = shmobile_smp_apmu_cpu_kill(ac - &apmu_cpus[0]); + + return ret < 0 ? ret : 0; +} + +static const struct mcpm_platform_ops apmu_pm_power_ops = { + .power_up = apmu_power_up, + .power_down = apmu_power_down, + .power_down_finish = apmu_power_down_finish, +}; + +static int __init shmobile_smp_apmu_mcpm_hook(void) +{ + int ret; + + mcpm_smp_set_ops(); + + ret = mcpm_platform_register(&apmu_pm_power_ops); + if (!ret) { + if (cci_probed()) + mcpm_sync_init(apmu_power_up_setup); + + pr_info("APMU MCPM power management initialized\n"); + } + return ret; +} +#else +static inline int shmobile_smp_apmu_mcpm_hook(void) { return 0; } +#endif + +static int __init shmobile_smp_apmu_cci_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); + if (node && of_device_is_available(node)) + return shmobile_smp_apmu_mcpm_hook(); + + return -ENODEV; +} --- 0001/arch/arm/mach-shmobile/platsmp.c +++ work/arch/arm/mach-shmobile/platsmp.c 2014-02-27 00:57:50.000000000 +0900 @@ -28,6 +28,10 @@ void shmobile_smp_hook(unsigned int cpu, shmobile_smp_fn[cpu] = fn; shmobile_smp_arg[cpu] = arg; flush_cache_all(); + + sync_cache_w(&shmobile_smp_mpidr[cpu]); + sync_cache_w(&shmobile_smp_fn[cpu]); + sync_cache_w(&shmobile_smp_arg[cpu]); } #ifdef CONFIG_HOTPLUG_CPU