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Wed, 2 Jul 2014 20:26:18 -0700 Date: Thu, 3 Jul 2014 11:26:17 +0800 From: Shawn Guo To: Fabio Estevam Subject: Re: [PATCH 4/5] ARM: imx: clk-gate2: Use post decrement for share_count Message-ID: <20140703032615.GE16176@dragon> References: <1404194129-25543-1-git-send-email-festevam@gmail.com> <1404194129-25543-4-git-send-email-festevam@gmail.com> <20140701115252.GM14471@dragon> <20140702043508.GA16176@dragon> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199002)(189002)(24454002)(51704005)(80022001)(76482001)(79102001)(20776003)(86362001)(97756001)(26826002)(84676001)(77982001)(64706001)(76176999)(54356999)(1411001)(50986999)(74662001)(31966008)(33716001)(83506001)(81156004)(99396002)(106466001)(69596002)(97736001)(46102001)(74502001)(21056001)(68736004)(107046002)(50466002)(47776003)(92566001)(102836001)(57986006)(92726001)(83322001)(85306003)(19580395003)(19580405001)(6806004)(44976005)(33656002)(81342001)(46406003)(4396001)(23726002)(83072002)(105606002)(95666004)(104016002)(93886003)(85852003)(81542001)(87936001); DIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB242; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 0261CCEEDF Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140702_202651_027131_3D521280 X-CRM114-Status: GOOD ( 25.92 ) X-Spam-Score: -2.7 (--) Cc: Fabio Estevam , Nicolin Chen , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Wed, Jul 02, 2014 at 11:27:21AM -0300, Fabio Estevam wrote: > > From 0ed4b3edc661c63f86c914ea3c6deb3af3438151 Mon Sep 17 00:00:00 2001 > > From: Shawn Guo > > Date: Wed, 2 Jul 2014 11:32:06 +0800 > > Subject: [PATCH] ARM: imx: fix shared gate clock to have its own enable count > > > > Let's say clock A and B are two gate clocks that share the same register > > bit in hardware. Therefore they should be registered as shared gate > > clocks with imx_clk_gate2_shared(). > > > > In the current implementation, clk_enable(A) call will have share_count > > become 1. If clk_disable(B) is called right after that, the register > > bit will be cleared to gate off the clocks. This is unexpected. The > > cause for that is there is no enable count tracking for clock A and B > > respectively. > > > > The patch fixes the issue by adding enable_count into clk_gate2, and > > tracks it prior to share_count in .enable and .disable. Also, > > .is_enabled is fixed to report enable state instead of hardware state > > in case of shared gate clock. > > > > Reported-by: Fabio Estevam > > Cc: > > Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") > > No need to Cc stable on this one as the this commit did not reach stable. Yes, you're right. ... > > @@ -67,6 +71,9 @@ static void clk_gate2_disable(struct clk_hw *hw) > > > > spin_lock_irqsave(gate->lock, flags); > > > > + if (--gate->enable_count > 0) > > + goto out; > > All these pre-decrement look buggy because enable_count and > share_count are 'unsigned int'. > > If share_count is 0 and then you decrement it, it will still be > greater than zero. > --(*gate->share_count) > 0 and --gate->enable_count > 0 are always true. Hmm, clk_gate2_disable() should never be called with a zero share_count. I will add a check for that. > I have tried to make share_count and enable_count as 'int'. Then it > resulted CGR5 as > 0FFFCFFF, which still leaves ssi1 and ssi3 enabled (I have locally > made ssi a shared clock now) Right. The patch did not fix the problem correctly. I just started it over again with the one below. Can you please test it? Thanks. Shawn ---8<------------------- From e057f4c129e77639372f2b4a3b9eb8a9de2095f8 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 2 Jul 2014 11:32:06 +0800 Subject: [PATCH] ARM: imx: fix shared gate clock to be added ... Reported-by: Fabio Estevam Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-gate2.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 4ba587da89d2..3aa9c74d13be 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -67,8 +67,12 @@ static void clk_gate2_disable(struct clk_hw *hw) spin_lock_irqsave(gate->lock, flags); - if (gate->share_count && --(*gate->share_count) > 0) - goto out; + if (gate->share_count) { + if (WARN_ON(*gate->share_count == 0)) + goto out; + else if (--(*gate->share_count) > 0) + goto out; + } reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); @@ -78,19 +82,26 @@ out: spin_unlock_irqrestore(gate->lock, flags); } -static int clk_gate2_is_enabled(struct clk_hw *hw) +static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) { - u32 reg; - struct clk_gate2 *gate = to_clk_gate2(hw); + u32 val = readl(reg); - reg = readl(gate->reg); - - if (((reg >> gate->bit_idx) & 1) == 1) + if (((val >> bit_idx) & 1) == 1) return 1; return 0; } +static int clk_gate2_is_enabled(struct clk_hw *hw) +{ + struct clk_gate2 *gate = to_clk_gate2(hw); + + if (gate->share_count) + return !!(*gate->share_count); + else + return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); +} + static struct clk_ops clk_gate2_ops = { .enable = clk_gate2_enable, .disable = clk_gate2_disable, @@ -116,6 +127,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, gate->bit_idx = bit_idx; gate->flags = clk_gate2_flags; gate->lock = lock; + + if (share_count) + *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0; gate->share_count = share_count; init.name = name;