diff mbox

socfpga/sockit ethernet problems

Message ID 20140707214340.GA29061@amd.pavel.ucw.cz (mailing list archive)
State New, archived
Headers show

Commit Message

Pavel Machek July 7, 2014, 9:43 p.m. UTC
Hi!

> > I made this, but ethernet problems I currently see are not frequent
> > enough to allow easy debugging. If link takes long to  estabilish for
> > you, could you test the patch below?

> > +static int ksz9021rn_phy_fixup(struct phy_device *phydev)
> > +{
> > +        if (IS_BUILTIN(CONFIG_PHYLIB)) {
> > +		printk("------------- running phy fixup\n");
> > +
> > +                /* min rx data delay */
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			  0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SKEW);
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
> > +
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			  0x8000 | MICREL_KSZ9021_RGMII_TX_DATA_PAD_SKEW);
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
> > +
> > +                /* max rx/tx clock delay, min rx/tx control delay */
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			  0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SKEW);
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			  MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SKEW);
> > +        }
> > +
> > +        return 0;
> > +}
> > +
> 
> All of this stuff is not needed as it's already taken care of by the
> Micrel phy driver. The clock skew values are now represented in the DTS.
> Please look at:
> 
> Documentation/devicetree/bindings/net/micrel-ksz90x1.txt

Aah, thanks for the pointer. 

At least socfpga_cyclone5_socrates.dts is in the mainline, but it does
not have any skew configuration. That may explain why the board seems
to have problems with ethernet... (or not).

Are there suitable default values?

u-boot uses these defaults:

include/configs/socfpga_common.h:#define CONFIG_KSZ9021_CLK_SKEW_VAL
0xf0f0
include/configs/socfpga_common.h:#define CONFIG_KSZ9021_DATA_SKEW_VAL
0x0

...that should correspond to txc-skew-ps == rxc-skew-ps == 3000, all
other skew values == 0?

Could someone with socrates board and network problems test if this
makes any difference?

Signed-off-by: Pavel Machek <pavel@denx.de>

Comments

Steffen Trumtrar July 8, 2014, 7:19 a.m. UTC | #1
Hi!

Pavel Machek <pavel@denx.de> writes:
> Hi!
>
>> > I made this, but ethernet problems I currently see are not frequent
>> > enough to allow easy debugging. If link takes long to  estabilish for
>> > you, could you test the patch below?
>
>> > +static int ksz9021rn_phy_fixup(struct phy_device *phydev)
>> > +{
>> > +        if (IS_BUILTIN(CONFIG_PHYLIB)) {
>> > +		printk("------------- running phy fixup\n");
>> > +
>> > +                /* min rx data delay */
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
>> > +			  0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SKEW);
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
>> > +
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
>> > +			  0x8000 | MICREL_KSZ9021_RGMII_TX_DATA_PAD_SKEW);
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
>> > +
>> > +                /* max rx/tx clock delay, min rx/tx control delay */
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
>> > +			  0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SKEW);
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
>> > +                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
>> > +			  MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SKEW);
>> > +        }
>> > +
>> > +        return 0;
>> > +}
>> > +
>> 
>> All of this stuff is not needed as it's already taken care of by the
>> Micrel phy driver. The clock skew values are now represented in the DTS.
>> Please look at:
>> 
>> Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
>
> Aah, thanks for the pointer. 
>
> At least socfpga_cyclone5_socrates.dts is in the mainline, but it does
> not have any skew configuration. That may explain why the board seems
> to have problems with ethernet... (or not).
>

The socrates does not have these values, because it does not have a
Micrel PHY...

> Are there suitable default values?
>
> u-boot uses these defaults:
>
> include/configs/socfpga_common.h:#define CONFIG_KSZ9021_CLK_SKEW_VAL
> 0xf0f0
> include/configs/socfpga_common.h:#define CONFIG_KSZ9021_DATA_SKEW_VAL
> 0x0
>
> ...that should correspond to txc-skew-ps == rxc-skew-ps == 3000, all
> other skew values == 0?
>
> Could someone with socrates board and network problems test if this
> makes any difference?
>

...so, would this even apply to the socrates then?

Regards,
Steffen
Stefan Roese July 8, 2014, 7:47 a.m. UTC | #2
Hi!

On 07.07.2014 23:43, Pavel Machek wrote:
>> All of this stuff is not needed as it's already taken care of by the
>> Micrel phy driver. The clock skew values are now represented in the DTS.
>> Please look at:
>>
>> Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
>
> Aah, thanks for the pointer.
>
> At least socfpga_cyclone5_socrates.dts is in the mainline, but it does
> not have any skew configuration. That may explain why the board seems
> to have problems with ethernet... (or not).
>
> Are there suitable default values?
>
> u-boot uses these defaults:
>
> include/configs/socfpga_common.h:#define CONFIG_KSZ9021_CLK_SKEW_VAL
> 0xf0f0
> include/configs/socfpga_common.h:#define CONFIG_KSZ9021_DATA_SKEW_VAL
> 0x0
>
> ...that should correspond to txc-skew-ps == rxc-skew-ps == 3000, all
> other skew values == 0?
>
> Could someone with socrates board and network problems test if this
> makes any difference?

SoCrates uses a different PHY, the Lantiq PEF7071 (PHY11G). So those dts 
additions have no effect on SoCrates.

Thanks,
Stefan
Pavel Machek July 14, 2014, 12:34 p.m. UTC | #3
Hi!

> >Are there suitable default values?
> >
> >u-boot uses these defaults:
> >
> >include/configs/socfpga_common.h:#define CONFIG_KSZ9021_CLK_SKEW_VAL
> >0xf0f0
> >include/configs/socfpga_common.h:#define CONFIG_KSZ9021_DATA_SKEW_VAL
> >0x0
> >
> >...that should correspond to txc-skew-ps == rxc-skew-ps == 3000, all
> >other skew values == 0?
> >
> >Could someone with socrates board and network problems test if this
> >makes any difference?
> 
> SoCrates uses a different PHY, the Lantiq PEF7071 (PHY11G). So those
> dts additions have no effect on SoCrates.

Oops, I guess I was confused.
									Pavel
Pavel Machek July 14, 2014, 12:36 p.m. UTC | #4
Hi!

> >> All of this stuff is not needed as it's already taken care of by the
> >> Micrel phy driver. The clock skew values are now represented in the DTS.
> >> Please look at:
> >> 
> >> Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
> >
> > Aah, thanks for the pointer. 
> >
> > At least socfpga_cyclone5_socrates.dts is in the mainline, but it does
> > not have any skew configuration. That may explain why the board seems
> > to have problems with ethernet... (or not).
> 
> The socrates does not have these values, because it does not have a
> Micrel PHY...

Hmm, that is not it, then :-(. Is there any other setup that needs to
be done? Because from the experience with the socrates boards, they
are quite picky about cabling used.

Thanks and best regards,
									Pavel
diff mbox

Patch

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index a1814b4..eba8eea 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -34,6 +34,16 @@ 
 
 &gmac1 {
 	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <3000>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <3000>;
 };
 
 &i2c0 {