From patchwork Tue Jul 29 12:32:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Fuzzey X-Patchwork-Id: 4640301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5B109C0338 for ; Tue, 29 Jul 2014 12:35:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7F8F420115 for ; Tue, 29 Jul 2014 12:35:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5424200FF for ; Tue, 29 Jul 2014 12:35:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XC6bL-0006mi-0h; Tue, 29 Jul 2014 12:33:55 +0000 Received: from mta1.parkeon.com ([91.121.43.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XC6an-0006Bq-O8 for linux-arm-kernel@lists.infradead.org; Tue, 29 Jul 2014 12:33:26 +0000 Received: from ip71.parkeon.com ([213.152.31.71] helo=mta2.parkeon.com) by mta1.parkeon.com with esmtp (Exim 4.76) (envelope-from ) id 1XC6aR-0002rF-6u; Tue, 29 Jul 2014 14:32:59 +0200 Received: from mail.besancon.parkeon.com ([10.32.16.23]) by mta2.parkeon.com with esmtp (Exim 4.77) (envelope-from ) id 1XC6aP-0004kM-D2; Tue, 29 Jul 2014 14:32:57 +0200 Received: from [10.32.51.161] (port=47429 helo=[127.0.0.1]) by mail.besancon.parkeon.com with esmtp (Exim 4.71) (envelope-from ) id 1XC6aR-0002AJ-3A; Tue, 29 Jul 2014 14:32:59 +0200 Subject: [PATCH 1/4] ARM: perf: Set suniden bit. To: Shawn Guao , Will Deacon , linux-arm-kernel@lists.infradead.org From: Martin Fuzzey Date: Tue, 29 Jul 2014 14:32:59 +0200 Message-ID: <20140729123259.13347.33212.stgit@localhost> In-Reply-To: <20140729123256.13347.79778.stgit@localhost> References: <20140729123256.13347.79778.stgit@localhost> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: by ClamAV at mta2.parkeon.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140729_053321_966276_1BB489B5 X-CRM114-Status: UNSURE ( 9.95 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Counters other than the CPU cycle counter only work if the security module SUNIDEN bit is set. Without this: # perf stat -e cycles,instructions sleep 1 Performance counter stats for 'sleep 1': 14606094 cycles # 0.000 GHz 0 instructions # 0.00 insns per cycle Some platforms (eg i.MX53) may also need additional platform specific setup. Signed-off-by: Martin Fuzzey --- arch/arm/include/asm/pmu.h | 7 +++++++ arch/arm/kernel/perf_event_v7.c | 23 +++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index ae1919b..0bd181f 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -60,6 +60,13 @@ struct pmu_hw_events { * read/modify/write sequences. */ raw_spinlock_t pmu_lock; + + /* + * Bits indicating any CPU or platform specific activations that have + * been done so we can undo them when stopping + */ + unsigned int activated_flags; + #define ARM_PMU_ACTIVATED_SECURE_DEBUG (1 << 0) }; struct arm_pmu { diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 1d37568..91a41bd 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1377,12 +1377,26 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) return IRQ_HANDLED; } +#define SDER_SUNIDEN (1 << 1) + static void armv7pmu_start(struct arm_pmu *cpu_pmu) { unsigned long flags; struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + u32 sder; raw_spin_lock_irqsave(&events->pmu_lock, flags); + + /* Counters other than cycle counter require SUNIDEN bit set */ + asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (sder)); + if (sder & SDER_SUNIDEN) { + events->activated_flags &= ~ARM_PMU_ACTIVATED_SECURE_DEBUG; + } else { + sder |= SDER_SUNIDEN; + asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (sder)); + events->activated_flags |= ARM_PMU_ACTIVATED_SECURE_DEBUG; + } + /* Enable all counters */ armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); raw_spin_unlock_irqrestore(&events->pmu_lock, flags); @@ -1392,8 +1406,17 @@ static void armv7pmu_stop(struct arm_pmu *cpu_pmu) { unsigned long flags; struct pmu_hw_events *events = cpu_pmu->get_hw_events(); + u32 sder; raw_spin_lock_irqsave(&events->pmu_lock, flags); + + if (events->activated_flags & ARM_PMU_ACTIVATED_SECURE_DEBUG) { + asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (sder)); + sder &= ~SDER_SUNIDEN; + asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (sder)); + events->activated_flags &= ~ARM_PMU_ACTIVATED_SECURE_DEBUG; + } + /* Disable all counters */ armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); raw_spin_unlock_irqrestore(&events->pmu_lock, flags);