From patchwork Tue Jul 29 12:33:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Fuzzey X-Patchwork-Id: 4640281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E09B69F36A for ; Tue, 29 Jul 2014 12:35:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0049D20115 for ; Tue, 29 Jul 2014 12:35:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 488A920120 for ; Tue, 29 Jul 2014 12:35:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XC6b9-0006cc-4y; Tue, 29 Jul 2014 12:33:43 +0000 Received: from mta1.parkeon.com ([91.121.43.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XC6an-0006DR-O1 for linux-arm-kernel@lists.infradead.org; Tue, 29 Jul 2014 12:33:27 +0000 Received: from ip71.parkeon.com ([213.152.31.71] helo=mta2.parkeon.com) by mta1.parkeon.com with esmtp (Exim 4.76) (envelope-from ) id 1XC6aV-0002sJ-Cj; Tue, 29 Jul 2014 14:33:03 +0200 Received: from mail.besancon.parkeon.com ([10.32.16.23]) by mta2.parkeon.com with esmtp (Exim 4.77) (envelope-from ) id 1XC6aT-0004kY-Iq; Tue, 29 Jul 2014 14:33:01 +0200 Received: from [10.32.51.161] (port=47431 helo=[127.0.0.1]) by mail.besancon.parkeon.com with esmtp (Exim 4.71) (envelope-from ) id 1XC6aV-0002AW-99; Tue, 29 Jul 2014 14:33:03 +0200 Subject: [PATCH 3/4] ARM: i.MX53: Add Soc specific PMU setup. To: Shawn Guao , Will Deacon , linux-arm-kernel@lists.infradead.org From: Martin Fuzzey Date: Tue, 29 Jul 2014 14:33:03 +0200 Message-ID: <20140729123303.13347.12389.stgit@localhost> In-Reply-To: <20140729123256.13347.79778.stgit@localhost> References: <20140729123256.13347.79778.stgit@localhost> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: by ClamAV at mta2.parkeon.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140729_053321_977003_861CE3E4 X-CRM114-Status: GOOD ( 10.85 ) X-Spam-Score: -0.7 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On i.MX53 it is necessary to set the DBG_EN bit in the platform GPC register to enable access to PMU counters other than the cycle counter. Signed-off-by: Martin Fuzzey --- arch/arm/mach-imx/mach-imx53.c | 55 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 2bad387..b2cc235 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -19,16 +19,69 @@ #include #include #include +#include #include "common.h" #include "hardware.h" #include "mx53.h" +#include "crm-regs-imx5.h" + +#define GPC_DBG_EN (1 << 16) + +static void imx53_pmu_start(struct arm_pmu *arm_pmu) +{ + unsigned long flags; + struct pmu_hw_events *events = arm_pmu->get_hw_events(); + u32 gpc; + + raw_spin_lock_irqsave(&events->pmu_lock, flags); + + gpc = __raw_readl(MXC_CORTEXA8_PLAT_GPC); + if (gpc & GPC_DBG_EN) { + events->activated_flags &= ~ARM_PMU_ACTIVATED_PLATFORM; + } else { + gpc |= GPC_DBG_EN; + __raw_writel(gpc, MXC_CORTEXA8_PLAT_GPC); + events->activated_flags |= ARM_PMU_ACTIVATED_PLATFORM; + } + + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + +static void imx53_pmu_stop(struct arm_pmu *arm_pmu) +{ + unsigned long flags; + struct pmu_hw_events *events = arm_pmu->get_hw_events(); + u32 gpc; + + raw_spin_lock_irqsave(&events->pmu_lock, flags); + + if (events->activated_flags & ARM_PMU_ACTIVATED_PLATFORM) { + gpc = __raw_readl(MXC_CORTEXA8_PLAT_GPC); + gpc &= ~GPC_DBG_EN; + __raw_writel(gpc, MXC_CORTEXA8_PLAT_GPC); + events->activated_flags &= ~ARM_PMU_ACTIVATED_PLATFORM; + } + + raw_spin_unlock_irqrestore(&events->pmu_lock, flags); +} + +static struct arm_pmu_platdata imx53_pmu_platdata = { + .start = imx53_pmu_start, + .stop = imx53_pmu_stop, +}; + +static struct of_dev_auxdata imx53_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,cortex-a8-pmu", 0, "arm-pmu", &imx53_pmu_platdata), + {} +}; static void __init imx53_dt_init(void) { mxc_arch_reset_init_dt(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + imx53_auxdata_lookup, NULL); } static const char *imx53_dt_board_compat[] __initconst = {