From patchwork Tue Aug 5 14:48:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Fuzzey X-Patchwork-Id: 4679411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AAF52C033A for ; Tue, 5 Aug 2014 14:51:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 11A95201CD for ; Tue, 5 Aug 2014 14:51:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 556722018B for ; Tue, 5 Aug 2014 14:51:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XEg3A-00069a-VP; Tue, 05 Aug 2014 14:49:16 +0000 Received: from mta1.parkeon.com ([91.121.43.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XEg2s-00063A-Gq for linux-arm-kernel@lists.infradead.org; Tue, 05 Aug 2014 14:49:00 +0000 Received: from ip71.parkeon.com ([213.152.31.71] helo=mta2.parkeon.com) by mta1.parkeon.com with esmtp (Exim 4.76) (envelope-from ) id 1XEg2Y-0004hR-5z; Tue, 05 Aug 2014 16:48:38 +0200 Received: from mail.besancon.parkeon.com ([10.32.16.23]) by mta2.parkeon.com with esmtp (Exim 4.77) (envelope-from ) id 1XEg2W-0004aD-1I; Tue, 05 Aug 2014 16:48:36 +0200 Received: from [10.32.51.161] (port=40318 helo=[127.0.0.1]) by mail.besancon.parkeon.com with esmtp (Exim 4.71) (envelope-from ) id 1XEg2Y-0004cr-1p; Tue, 05 Aug 2014 16:48:38 +0200 Subject: [PATCH V2 3/4] ARM: i.MX53: Add Soc specific PMU setup. To: Shawn Guao , Will Deacon , linux-arm-kernel@lists.infradead.org From: Martin Fuzzey Date: Tue, 05 Aug 2014 16:48:38 +0200 Message-ID: <20140805144837.25462.15001.stgit@localhost> In-Reply-To: <20140805144831.25462.18149.stgit@localhost> References: <20140805144831.25462.18149.stgit@localhost> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: by ClamAV at mta2.parkeon.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140805_074858_721618_D81A52A7 X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -0.7 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On i.MX53 it is necessary to set the DBG_EN bit in the platform GPC register to enable access to PMU counters other than the cycle counter. Signed-off-by: Martin Fuzzey --- arch/arm/mach-imx/mach-imx53.c | 50 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 2bad387..74f6bf3 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -19,16 +19,64 @@ #include #include #include +#include #include "common.h" +#include "crm-regs-imx5.h" #include "hardware.h" #include "mx53.h" +#define GPC_DBG_EN (1 << 16) + +static int imx53_pmu_resume(struct device *dev) +{ + struct arm_pmu *arm_pmu = dev_get_drvdata(dev); + u32 gpc; + + gpc = __raw_readl(MXC_CORTEXA8_PLAT_GPC); + if (gpc & GPC_DBG_EN) { + arm_pmu->activated_flags.platform_enabled = 0; + } else { + gpc |= GPC_DBG_EN; + __raw_writel(gpc, MXC_CORTEXA8_PLAT_GPC); + arm_pmu->activated_flags.platform_enabled = 1; + } + + return 0; +} + +static int imx53_pmu_suspend(struct device *dev) +{ + struct arm_pmu *arm_pmu = dev_get_drvdata(dev); + u32 gpc; + + if (arm_pmu->activated_flags.platform_enabled) { + gpc = __raw_readl(MXC_CORTEXA8_PLAT_GPC); + gpc &= ~GPC_DBG_EN; + __raw_writel(gpc, MXC_CORTEXA8_PLAT_GPC); + arm_pmu->activated_flags.platform_enabled = 0; + } + + return 0; +} + + +static struct arm_pmu_platdata imx53_pmu_platdata = { + .runtime_resume = imx53_pmu_resume, + .runtime_suspend = imx53_pmu_suspend, +}; + +static struct of_dev_auxdata imx53_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,cortex-a8-pmu", 0, "arm-pmu", &imx53_pmu_platdata), + {} +}; + static void __init imx53_dt_init(void) { mxc_arch_reset_init_dt(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + imx53_auxdata_lookup, NULL); } static const char *imx53_dt_board_compat[] __initconst = {