From patchwork Wed Apr 1 09:22:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 6138591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 43A99BF4A6 for ; Wed, 1 Apr 2015 09:25:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5970F202EB for ; Wed, 1 Apr 2015 09:25:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 583E8202AE for ; Wed, 1 Apr 2015 09:25:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YdErW-0004cP-1h; Wed, 01 Apr 2015 09:23:02 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YdErQ-0004MO-BR for linux-arm-kernel@lists.infradead.org; Wed, 01 Apr 2015 09:22:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69C9527; Wed, 1 Apr 2015 02:22:32 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D421E3F212; Wed, 1 Apr 2015 02:22:32 -0700 (PDT) Date: Wed, 1 Apr 2015 10:22:29 +0100 From: Will Deacon To: Paul Walmsley Subject: Re: [PATCH] arm64: fix midr range for Cortex-A57 erratum 832075 Message-ID: <20150401092229.GC1552@arm.com> References: <1427833848-12188-1-git-send-email-byan@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150401_022256_502977_47E90012 X-CRM114-Status: GOOD ( 17.16 ) X-Spam-Score: -5.0 (-----) Cc: Bo Yan , Andre Przywara , "linux-arm-kernel@lists.infradead.org" , "pwalmsley@nvidia.com" , Catalin Marinas X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Mar 31, 2015 at 10:17:21PM +0100, Paul Walmsley wrote: > On Tue, 31 Mar 2015, Bo Yan wrote: > > > Register MIDR_EL1 is masked to get variant and revision fields, then > > compared against midr_range_min and midr_range_max when checking > > whether CPU is affected by any particular erratum. However, variant > > and revision fields in MIDR_EL1 are separated by 16 bits, so the min > > and max of midr range should be constructed accordingly, otherwise > > the patch will not be applied when variant field is non-0. > > > > Signed-off-by: Bo Yan > > --- > > arch/arm64/kernel/cpu_errata.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > > index fa62637e63a8..7838f1578019 100644 > > --- a/arch/arm64/kernel/cpu_errata.c > > +++ b/arch/arm64/kernel/cpu_errata.c > > @@ -88,7 +88,7 @@ struct arm64_cpu_capabilities arm64_errata[] = { > > /* Cortex-A57 r0p0 - r1p2 */ > > .desc = "ARM erratum 832075", > > .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, > > - MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12), > > + MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x100002), > > }, > > #endif > > { > > -- > > 2.1.4 > > Reviewed-by: Paul Walmsley > > Reviewed against DDI0488G section 4.3.1 "Main ID Register, EL1". Looks > like a cut-and-paste error from the A53 workarounds. Thanks guys, I agree that this is a bug. I'll apply this, but using an explicit shift to set the variant (tweaked version below). Will --->8 Acked-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a66f4fa4d541..c998345a052f 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -70,7 +70,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { /* Cortex-A57 r0p0 - r1p2 */ .desc = "ARM erratum 832075", .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, - MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12), + MIDR_RANGE(MIDR_CORTEX_A57, 0x00, (1 << MIDR_VARIANT_SHIFT) | 2, }, #endif {