From patchwork Mon May 18 22:37:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 6432561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7266A9F4DD for ; Mon, 18 May 2015 22:41:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6F8B3203B7 for ; Mon, 18 May 2015 22:41:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 749B5203AB for ; Mon, 18 May 2015 22:41:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuTgL-0007A9-Jx; Mon, 18 May 2015 22:38:45 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuTfq-0006bP-Jx for linux-arm-kernel@lists.infradead.org; Mon, 18 May 2015 22:38:15 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id A46E68026; Mon, 18 May 2015 22:39:14 +0000 (UTC) Date: Mon, 18 May 2015 15:37:50 -0700 From: Tony Lindgren To: linux-omap@vger.kernel.org Subject: Re: [PATCH 1/2] ARM: OMAP3: Add support for configuring MMC pins as GPIO pins Message-ID: <20150518223749.GL10274@atomide.com> References: <1430528752-316-1-git-send-email-tony@atomide.com> <1430528752-316-2-git-send-email-tony@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1430528752-316-2-git-send-email-tony@atomide.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150518_153814_788523_97F9A434 X-CRM114-Status: GOOD ( 16.37 ) X-Spam-Score: 0.0 (/) Cc: Tim Nordell , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP * Tony Lindgren [150501 18:07]: > +/* > + * Configures GPIOs 126 to 129 to 1.8V mode instead of 3.0V > + * mode for MMC1 in case bootloader did not configure things. > + * Note that if the pins are used for MMC1, pbias-regulator > + * manages the IO voltage. > + */ > +static void __init omap3_gpio126_129(void) > +{ > + u32 reg; > + > + reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); > + reg &= ~OMAP343X_PBIASLITEVMODE1; > + reg |= OMAP343X_PBIASLITEPWRDNZ1; > + omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE); > + if (cpu_is_omap3630()) { > + reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); > + reg |= OMAP36XX_GPIO_IO_PWRDNZ; > + omap_ctrl_writel(reg, OMAP34XX_CONTROL_WKUP_CTRL); > + } > +} > + This seems to not include GPIO 128 as pointed out by Tim Nordell, so patch with updated naming below. Regards, Tony 8< ------------------ From: Tony Lindgren Date: Wed, 13 May 2015 11:42:59 -0700 Subject: [PATCH] ARM: OMAP3: Add support for configuring MMC pins as GPIO pins Some devices are using the MMC1 pins 4..8 as GPIO pins, and in this case they need to be configured for 1.8V IO voltage if not done by the bootloader as otherwise some devices like smsc911x won't work properly. Let's also make sure this register is saved and restored for idle. Cc: Tim Nordell Signed-off-by: Tony Lindgren --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -112,6 +112,7 @@ struct omap3_control_regs { u32 csirxfe; u32 iva2_bootaddr; u32 iva2_bootmod; + u32 wkup_ctrl; u32 debobs_0; u32 debobs_1; u32 debobs_2; @@ -455,6 +456,7 @@ void omap3_control_save_context(void) omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); control_context.iva2_bootmod = omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); + control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); @@ -512,6 +514,7 @@ void omap3_control_restore_context(void) OMAP343X_CONTROL_IVA2_BOOTADDR); omap_ctrl_writel(control_context.iva2_bootmod, OMAP343X_CONTROL_IVA2_BOOTMOD); + omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL); omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -231,6 +231,9 @@ #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) /* 34xx GENERAL_WKUP register offsets */ +#define OMAP34XX_CONTROL_WKUP_CTRL (OMAP343X_CONTROL_GENERAL_WKUP - 0x4) +#define OMAP36XX_GPIO_IO_PWRDNZ BIT(6) + #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ 0x008 + (i)) #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -44,6 +44,27 @@ static void __init omap2420_n8x0_legacy_init(void) #endif #ifdef CONFIG_ARCH_OMAP3 +/* + * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V + * mode for MMC1 in case bootloader did not configure things. + * Note that if the pins are used for MMC1, pbias-regulator + * manages the IO voltage. + */ +static void __init omap3_gpio126_127_129(void) +{ + u32 reg; + + reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); + reg &= ~OMAP343X_PBIASLITEVMODE1; + reg |= OMAP343X_PBIASLITEPWRDNZ1; + omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE); + if (cpu_is_omap3630()) { + reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); + reg |= OMAP36XX_GPIO_IO_PWRDNZ; + omap_ctrl_writel(reg, OMAP34XX_CONTROL_WKUP_CTRL); + } +} + static void __init hsmmc2_internal_input_clk(void) { u32 reg; @@ -356,6 +377,7 @@ static struct pdata_init pdata_quirks[] __initdata = { { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, }, { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, }, + { "logicpd,dm3730-torpedo-devkit", omap3_gpio126_127_129, }, { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, { "ti,am3517-evm", am3517_evm_legacy_init, }, { "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },