From patchwork Sat Aug 22 13:10:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 7055791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 733529F2B4 for ; Sat, 22 Aug 2015 13:15:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3626B206A1 for ; Sat, 22 Aug 2015 13:15:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 298CB20460 for ; Sat, 22 Aug 2015 13:15:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZT8bd-0003tQ-OV; Sat, 22 Aug 2015 13:13:09 +0000 Received: from mail-bn1bn0100.outbound.protection.outlook.com ([157.56.110.100] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZT8ba-0003cJ-Es for linux-arm-kernel@lists.infradead.org; Sat, 22 Aug 2015 13:13:07 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Robert.Richter@caviumnetworks.com; Received: from rric.localdomain (78.53.82.170) by BY1PR0701MB1611.namprd07.prod.outlook.com (10.162.110.152) with Microsoft SMTP Server (TLS) id 15.1.231.21; Sat, 22 Aug 2015 13:11:01 +0000 Date: Sat, 22 Aug 2015 15:10:50 +0200 From: Robert Richter To: Marc Zygnier , Will Deacon , Thomas Gleixner , Jason Cooper Subject: [PATCH] irqchip, gicv3-its, numa: Workaround for Cavium ThunderX erratum 23144 Message-ID: <20150822131050.GK1820@rric.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-Originating-IP: [78.53.82.170] X-ClientProxiedBy: AM2PR03CA0025.eurprd03.prod.outlook.com (25.160.207.35) To BY1PR0701MB1611.namprd07.prod.outlook.com (25.162.110.152) X-Microsoft-Exchange-Diagnostics: 1; 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BY1PR0701MB1611; 5:vNu4uK3+tRbFstVBNez5zE5oxtL2yCnnU2IDClHWNggLhByF1VueDi6DSmCj8ecnHPpQnVmVYjbv6xR9kQKvItD4w7hyMRGb3pt+yY5cHtxtQaoyYhg/aXLv61zQo/p+GG+2d07Dq9q3TB7j7TQ+Tg==; 24:aRlDnDXOLDkGCuJuVmq8ZJzW0lu7l+8lCvKRYJubivmgjJCcUZGrUVs3rKqHiPoy6fZiiQo+Qi28I5vqLsMRzdhJ3aE+p6rws++VPFGWE7o=; 20:gtqxR+7H5qOUON7+eiMy/4fezLpkq2ykTOne2C4+5IPR5rOdG1sqMiDFHi4ifFCrJm9/N1j+KXYqzOTjpmuP4w== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2015 13:11:01.1142 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1611 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150822_061306_786774_5D374723 X-CRM114-Status: GOOD ( 16.57 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Tirumalesh Chalamarla , Robert Richter , linux-kernel@vger.kernel.org, Ganapatrao Kulkarni Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch below adds a workaround for gicv3 in a numa environment. It is on top of my recent gicv3 errata patch submission v4 and Ganapat's arm64 numa patches for devicetree v5. Please comment. Thanks, -Robert From c432820451a46b8d1e299b8bfbfcdcb3b75340e7 Mon Sep 17 00:00:00 2001 From: Ganapatrao Kulkarni Date: Wed, 19 Aug 2015 23:40:05 +0530 Subject: [PATCH] irqchip, gicv3-its, numa: Workaround for Cavium ThunderX erratum 23144 This implements a workaround for gicv3-its erratum 23144 applicable for Cavium's ThunderX multinode systems. The erratum fixes the hang of ITS SYNC command by avoiding inter node io and collections/cpu mapping. This fix is only applicable for Cavium's ThunderX dual-socket platforms. Signed-off-by: Ganapatrao Kulkarni [ rric: Reworked errata code, added helper functions, updated commit message. ] Signed-off-by: Robert Richter --- arch/arm64/Kconfig | 14 +++++++++++ drivers/irqchip/irq-gic-common.c | 5 ++-- drivers/irqchip/irq-gic-v3-its.c | 54 ++++++++++++++++++++++++++++++++++------ 3 files changed, 64 insertions(+), 9 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3809187ed653..b92b7b70b29b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -421,6 +421,20 @@ config ARM64_ERRATUM_845719 If unsure, say Y. +config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + depends on NUMA + default y + help + Enable workaround for erratum 22375, 24313. + +config CAVIUM_ERRATUM_23144 + bool "Cavium erratum 23144" + depends on NUMA + default y + help + Enable workaround for erratum 23144. + config CAVIUM_ERRATUM_23154 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" depends on ARCH_THUNDER diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index ee789b07f2d1..1dfce64dbdac 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -24,11 +24,12 @@ void gic_check_capabilities(u32 iidr, const struct gic_capabilities *cap, void *data) { - for (; cap->desc; cap++) { + for (; cap->init; cap++) { if (cap->iidr != (cap->mask & iidr)) continue; cap->init(data); - pr_info("%s\n", cap->desc); + if (cap->desc) + pr_info("%s\n", cap->desc); } } diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 4bb135721e72..666be39f13a9 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -43,7 +43,8 @@ #include "irqchip.h" #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) -#define ITS_FLAGS_CAVIUM_THUNDERX (1ULL << 1) +#define ITS_WORKAROUND_CAVIUM_22375 (1ULL << 1) +#define ITS_WORKAROUND_CAVIUM_23144 (1ULL << 2) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -76,6 +77,7 @@ struct its_node { struct list_head its_device_list; u64 flags; u32 ite_size; + int numa_node; }; #define ITS_ITT_ALIGN SZ_256 @@ -609,11 +611,18 @@ static void its_eoi_irq(struct irq_data *d) static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) { - unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); + unsigned int cpu; struct its_device *its_dev = irq_data_get_irq_chip_data(d); struct its_collection *target_col; u32 id = its_get_event_id(d); + if (its_dev->its->flags & ITS_WORKAROUND_CAVIUM_23144) { + cpu = cpumask_any_and(mask_val, + cpumask_of_node(its_dev->its->numa_node)); + } else { + cpu = cpumask_any_and(mask_val, cpu_online_mask); + } + if (cpu >= nr_cpu_ids) return -EINVAL; @@ -845,7 +854,7 @@ static int its_alloc_tables(struct its_node *its) u64 typer; u32 ids; - if (its->flags & ITS_FLAGS_CAVIUM_THUNDERX) { + if (its->flags & ITS_WORKAROUND_CAVIUM_22375) { /* * erratum 22375: only alloc 8MB table size * erratum 24313: ignore memory access type @@ -1093,6 +1102,11 @@ static void its_cpu_init_lpis(void) dsb(sy); } +static inline int numa_node_id_early(void) +{ + return MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2); +} + static void its_cpu_init_collection(void) { struct its_node *its; @@ -1104,6 +1118,11 @@ static void its_cpu_init_collection(void) list_for_each_entry(its, &its_nodes, entry) { u64 target; + /* avoid cross node core and its mapping */ + if ((its->flags & ITS_WORKAROUND_CAVIUM_23144) && + its->numa_node != numa_node_id_early()) + continue; + /* * We now have to bind each collection to its target * redistributor. @@ -1372,9 +1391,15 @@ static void its_irq_domain_activate(struct irq_domain *domain, { struct its_device *its_dev = irq_data_get_irq_chip_data(d); u32 event = its_get_event_id(d); + unsigned int cpu; + + if (its_dev->its->flags & ITS_WORKAROUND_CAVIUM_23144) + cpu = cpumask_first(cpumask_of_node(its_dev->its->numa_node)); + else + cpu = cpumask_first(cpu_online_mask); /* Bind the LPI to the first possible CPU */ - its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask); + its_dev->event_map.col_map[event] = cpu; /* Map the GIC IRQ and event to the device */ its_send_mapvi(its_dev, d->hwirq, event); @@ -1457,16 +1482,31 @@ static int its_force_quiescent(void __iomem *base) } } +static inline int its_get_node_thunderx(struct its_node *its) +{ + return (its->phys_base >> 44) & 0x3; +} + static void its_enable_cavium_thunderx(void *data) { - struct its_node *its = data; + struct its_node __maybe_unused *its = data; - its->flags |= ITS_FLAGS_CAVIUM_THUNDERX; +#ifdef CONFIG_CAVIUM_ERRATUM_22375 + its->flags |= ITS_WORKAROUND_CAVIUM_22375; + pr_info("ITS: Enabling workaround for 22375, 24313\n"); +#endif + +#ifdef CONFIG_CAVIUM_ERRATUM_23144 + if (num_possible_nodes() > 1) { + its->numa_node = its_get_node_thunderx(its); + its->flags |= ITS_WORKAROUND_CAVIUM_23144; + pr_info("ITS: Enabling workaround for 23144\n"); + } +#endif } static const struct gic_capabilities its_errata[] = { { - .desc = "ITS: Cavium errata 22375, 24313", .iidr = 0xa100034c, /* ThunderX pass 1.x */ .mask = 0xffff0fff, .init = its_enable_cavium_thunderx,