From patchwork Mon Aug 24 09:39:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 7062921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CA0049F358 for ; Mon, 24 Aug 2015 09:42:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E14D820742 for ; Mon, 24 Aug 2015 09:42:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13A5E2073E for ; Mon, 24 Aug 2015 09:42:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZToEa-0006Vi-8K; Mon, 24 Aug 2015 09:40:08 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZToEW-0005LN-Nw for linux-arm-kernel@lists.infradead.org; Mon, 24 Aug 2015 09:40:05 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id ECA2A140E37; Mon, 24 Aug 2015 09:39:43 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id D4A93140E3A; Mon, 24 Aug 2015 09:39:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from codeaurora.org (unknown [202.46.23.62]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 97232140E37; Mon, 24 Aug 2015 09:39:39 +0000 (UTC) Date: Mon, 24 Aug 2015 15:09:34 +0530 From: Varadarajan Narayanan To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Varadarajan Narayanan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] dts: ipq40xx: Add the global counter node Message-ID: <20150824093934.GA26409@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150824_024004_816652_BFB1EB2E X-CRM114-Status: GOOD ( 21.69 ) X-Spam-Score: -3.8 (---) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Adding the dt data for the 56 global counter which supplies the count to the arm arch timers. Signed-off-by: Varadarajan Narayanan --- > Refer http://www.spinics.net/lists/linux-arm-msm/msg16660.html > > On Fri, Aug 21, 2015 at 09:21:33AM -0700, Bjorn Andersson > wrote: > > Most of the time when there's a device consuming one > register it turns out to be part of some larger hw block > and down the road things get complicated from the fact > that we mapped 4 bytes in the middle. > > Is this part of a larger block? Can we better implement > that as a simple-mfd or syscon? It is a part of larger block. However, we are ok with the default settings of the other registers. In a subsequent patch we will set a value in this register. Please let me know if I should still go for mfd/syscon Documentation/devicetree/bindings/clock/qca,gcnt.txt | 15 +++++++++++++++ arch/arm/boot/dts/qcom-ipq40xx.dtsi | 5 +++++ 2 files changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qca,gcnt.txt diff --git a/Documentation/devicetree/bindings/clock/qca,gcnt.txt b/Documentation/devicetree/bindings/clock/qca,gcnt.txt new file mode 100644 index 0000000..ccffc01 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qca,gcnt.txt @@ -0,0 +1,15 @@ +QCA Global Counter +------------------------------------------------ +Enable 56-bit global counter which supplies the count to the arm arch timers. + +Required properties : +- compatible : "qcom,qca-gcnt" + +- reg : shall contain base register location and length + +Example: + + counter { + compatible = "qcom,qca-gcnt"; + reg = <0x004a1000 0x4>; + }; diff --git a/arch/arm/boot/dts/qcom-ipq40xx.dtsi b/arch/arm/boot/dts/qcom-ipq40xx.dtsi index f572f38..76c55a3 100644 --- a/arch/arm/boot/dts/qcom-ipq40xx.dtsi +++ b/arch/arm/boot/dts/qcom-ipq40xx.dtsi @@ -62,6 +62,11 @@ <0x0b002000 0x1000>; }; + counter { + compatible = "qcom,qca-gcnt"; + reg = <0x004a1000 0x4>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 2 0xf08>,